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公开(公告)号：US12155743B2
公开(公告)日：2024-11-26
申请号：US17957414
申请日：2022-09-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunggeun Kim , Nakwon Lee , Jaehyun Park , Kyeongjoon Ko , Kangjik Kim , Seuk Son , Byunghyun Lim
IPC: H04L7/00
Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.
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Patent Agency Ranking
2.发明公开公开(公告)号：US20230141322A1
公开(公告)日：2023-05-11
申请号：US17985193
申请日：2022-11-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Sunggeun Kim , Hyeonju Lee , Seuk Son , Kangjik Kim , Jaehyun Park
CPC classification number: H03L7/0807 , H03L7/089 , H03L7/093 , H03L7/0998
Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
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公开(公告)号：US09698972B2
公开(公告)日：2017-07-04
申请号：US15048412
申请日：2016-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangjik Kim , Sanghune Park , Jaehyun Park , Jongshin Shin
CPC classification number: H04L7/04 , H03K5/08 , H03K5/1534 , H03K5/22 , H03K17/14 , H04L25/0272 , H04L25/0278 , H04L25/028
Abstract: Voltage mode drivers and an electronic apparatus having the same are provided. The voltage mode drivers may include a voltage regulator and a ripple compensation unit connected to an output terminal of the voltage regulator and configured to compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal input into the ripple compensation unit, generate a control signal when the current data bit is equal to the previous data bit, and apply a ground voltage to the output terminal in response to the control signal.
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公开(公告)号：US12068752B2
公开(公告)日：2024-08-20
申请号：US17985193
申请日：2022-11-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Sunggeun Kim , Hyeonju Lee , Seuk Son , Kangjik Kim , Jaehyun Park
CPC classification number: H03L7/0807 , H03L7/089 , H03L7/093 , H03L7/0998
Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
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公开(公告)号：US11740270B2
公开(公告)日：2023-08-29
申请号：US17943551
申请日：2022-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juyun Lee , Hanseok Kim , Jiyoung Kim , Jaehyun Park , Hyeonju Lee , Kangjik Kim , Sunggeun Kim , Seuk Son , Hobin Song , Nakwon Lee
CPC classification number: G01R25/04 , H03L7/085 , H03L7/0807
Abstract: An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.
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公开(公告)号：US20160294381A1
公开(公告)日：2016-10-06
申请号：US15048412
申请日：2016-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangjik Kim , Sanghune PARK , Jaehyun PARK , Jongshin SHIN
IPC: H03K17/28 , H03K5/1534 , H04L7/04 , H03K5/08
CPC classification number: H04L7/04 , H03K5/08 , H03K5/1534 , H03K5/22 , H03K17/14 , H04L25/0272 , H04L25/0278 , H04L25/028
Abstract: Voltage mode drivers and an electronic apparatus having the same are provided. The voltage mode drivers may include a voltage regulator and a ripple compensation unit connected to an output terminal of the voltage regulator and configured to compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal input into the ripple compensation unit, generate a control signal when the current data bit is equal to the previous data bit, and apply a ground voltage to the output terminal in response to the control signal.
Abstract translation: 提供电压模式驱动器和具有该电压模式驱动器的电子设备。 电压模式驱动器可以包括电压调节器和纹波补偿单元，其连接到电压调节器的输出端，并被配置为与时钟信号同步地将数据模式的当前数据位与数据模式的先前数据位进行比较 输入到纹波补偿单元，当当前数据位等于先前的数据位时产生控制信号，并且响应于控制信号向输出端施加接地电压。
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