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公开(公告)号：US20210174179A1
公开(公告)日：2021-06-10
申请号：US16989391
申请日：2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinook SONG , Daekyeung KIM , Junseok PARK , Joonho SONG , Sehwan LEE , Junwoo JANG , Yunkyo CHO
Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.
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公开(公告)号：US20190171930A1
公开(公告)日：2019-06-06
申请号：US16158660
申请日：2018-10-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sehwan LEE , Namjoon KIM , Joonho SONG , Junwoo JANG
Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network, the method includes determining operands from input feature maps and kernels, on which a convolution operation is to be performed, dispatching operand pairs combined from the determined operands to multipliers in a convolution operator, generating outputs by performing addition and accumulation operations with respect to results of multiplication operations, and obtaining pixel values of output feature maps corresponding to a result of the convolution operation based on the generated outputs.
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公开(公告)号：US20190138898A1
公开(公告)日：2019-05-09
申请号：US16107717
申请日：2018-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Joonho SONG , Sehwan LEE , Junwoo JANG
Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.
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4.发明申请公开(公告)号：US20220374651A1
公开(公告)日：2022-11-24
申请号：US17851704
申请日：2022-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： DINESH KUMAR YADAV , ANKUR DESHWAL , SAPTARSI DAS , Junwoo JANG , Sehwan LEE
Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.
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公开(公告)号：US20210248413A1
公开(公告)日：2021-08-12
申请号：US17243057
申请日：2021-04-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junwoo JANG
Abstract: A neural network apparatus includes one or more processors configured to acquire an input feature map and trained weights, generate a plurality of sub-feature maps by splitting the input feature map based on a dilation rate, generate a plurality of intermediate feature maps by performing a convolution operation between the plurality of sub-feature maps and the trained weights, and generate a dilated output feature map by merging the plurality of intermediate feature maps based on the dilation rate.
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Patent Agency Ranking
公开(公告)号：US20210064992A1
公开(公告)日：2021-03-04
申请号：US16803342
申请日：2020-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunsun PARK , Yoojin KIM , Hyeongseok YU , Sehwan LEE , Junwoo JANG
Abstract: A method of processing data includes identifying a sparsity of input data, based on valid information included in the input data, rearranging the input data, based on a form of the sparsity, and generating output data by processing the rearranged input data.
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公开(公告)号：US20210174178A1
公开(公告)日：2021-06-10
申请号：US16896500
申请日：2020-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunsun PARK , Yoojin KIM , Junwoo JANG
Abstract: A method of processing data includes manipulating input data based on a configuration of the input data and a configuration of hardware for processing the input data to generate manipulated data; rearranging the manipulated data based on sparsity of the manipulated data to generate rearranged data; and processing the rearranged data to generate output data.
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公开(公告)号：US20210117791A1
公开(公告)日：2021-04-22
申请号：US17112041
申请日：2020-12-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Joonho SONG , Sehwan LEE , Junwoo JANG
Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.
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9.发明申请公开(公告)号：US20200218936A1
公开(公告)日：2020-07-09
申请号：US16733314
申请日：2020-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： DINESH KUMAR YADAV , ANKUR DESHWAL , SAPTARSI DAS , Junwoo JANG , Sehwan LEE
Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.
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公开(公告)号：US20190138891A1
公开(公告)日：2019-05-09
申请号：US16106902
申请日：2018-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Namjoon KIM , Sehwan LEE , Junwoo JANG
Abstract: A neural network apparatus includes a plurality of node buffers connected to a node lane and configured to store input node data by a predetermined bit size; a plurality of weight buffers connected to a weight lane and configured to store weights; and one or more processors configured to: generate first and second split data by splitting the input node data by the predetermined bit size, store the first and second split data in the node buffers, output the first split data to an operation circuit for a neural network operation on an index-by-index basis, shift the second split data, and output the second split data to the operation circuit on the index-by-index basis.
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