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    Multi-port queueing cache and data processing system including the same
    4.
    发明授权
    Multi-port queueing cache and data processing system including the same 有权

    公开(公告)号：US12013786B2

    公开(公告)日：2024-06-18

    申请号：US18072929

    申请日：2022-12-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heonsoo Lee ,  Byungchul Hong ,  Junseok Park ,  Jaehun Chung

    IPC: G06F12/0862 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

    CPC classification number: G06F12/0862 ,  G06F9/3816 ,  G06F12/0261 ,  G06F12/0646

    Abstract: In some embodiments, a multi-port queueing cache includes a plurality of first ports, a plurality of second ports, a plurality of request handlers respectively coupled to the plurality of first ports, a cache storage unit coupled to the plurality of second ports, a reserve interface configured to exchange at least one address and at least one reserved cache line number, and a request interface configured to exchange the at least one reserved cache line number and at least one data. The reserve interface and the request interface are disposed between the plurality of request handlers and the cache storage unit. The cache storage unit includes a plurality of cache lines configured to store the plurality of data. The cache storage unit is configured to output a portion of the plurality of addresses, and receive a portion of the plurality of data corresponding to the portion of the plurality of addresses.

    Arithmetic apparatus, operating method thereof, and neural network processor
    6.
    发明授权
    Arithmetic apparatus, operating method thereof, and neural network processor 有权

    公开(公告)号：US12175208B2

    公开(公告)日：2024-12-24

    申请号：US16989391

    申请日：2020-08-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinook Song ,  Daekyeung Kim ,  Junseok Park ,  Joonho Song ,  Sehwan Lee ,  Junwoo Jang ,  Yunkyo Cho

    IPC: G06F7/544 ,  G06N3/063

    Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

    Neural network processor using dyadic weight matrix and operation method thereof
    8.
    发明授权
    Neural network processor using dyadic weight matrix and operation method thereof 有权

    公开(公告)号：US11562046B2

    公开(公告)日：2023-01-24

    申请号：US16675709

    申请日：2019-11-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junseok Park ,  Inyup Kang

    IPC: G06F17/00 ,  G06F17/16 ,  G06N3/063 ,  G06F7/44 ,  G06N3/08

    Abstract: An neural network (NN) processor includes an input feature map buffer configured to store an input feature matrix, a weight buffer configured to store a weight matrix trained in a form of a, a transform circuit configured to perform a Walsh-Hadamard transform on an input feature vector obtained from the input feature matrix and a weight vector included in the weight matrix to output a transformed input feature vector and a transformed weight vector, and an arithmetic circuit configured to perform an element-wise multiplication (EWM) on the transformed input feature vector and the transformed weight vector.

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