公开(公告)号：US11289456B2

公开(公告)日：2022-03-29

申请号：US16940045

申请日：2020-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohwan Lee ,  Jungsoo Byun

IPC: H01L25/065 ,  H01L23/04 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

公开(公告)号：US20210257305A1

公开(公告)日：2021-08-19

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo SHIM ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

公开(公告)号：US12015014B2

公开(公告)日：2024-06-18

申请号：US17679861

申请日：2022-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohwan Lee ,  Jungsoo Byun

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/041 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2225/06562

Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

公开(公告)号：US20210183817A1

公开(公告)日：2021-06-17

申请号：US16940045

申请日：2020-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohwan Lee ,  Jungsoo Byun

IPC: H01L25/065 ,  H01L23/04 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

公开(公告)号：US12218099B2

公开(公告)日：2025-02-04

申请号：US17392511

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo Byun ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip to some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips.

公开(公告)号：US11581263B2

公开(公告)日：2023-02-14

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo Shim ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/495 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

公开(公告)号：US11088115B2

公开(公告)日：2021-08-10

申请号：US16685575

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo Byun ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.