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1.发明授权Semiconductor memory device including non-volatile memory, cache memory, and computer system 有权包括非易失性存储器，高速缓冲存储器和计算机系统的半导体存储器件公开(公告)号：US09552256B2
公开(公告)日：2017-01-24
申请号：US14978538
申请日：2015-12-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-gyeum Kim , Hyeok-man Kwon , Young-jun Kwon , Ki-young Choi , Jun-whan Ahn
CPC classification number: G06F11/1068 , G06F11/1064 , G11C11/1653 , G11C11/1677 , G11C29/52
Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.
Abstract translation: 在一个实施例中，存储器件包括数据存储区域和纠错（ECC）区域。 数据存储区域被配置为存储第一数量的数据块。 ECC区域被配置为存储第二数量的ECC块。 第二数量的ECC块中的每一个被配置为存储ECC信息。 ECC块的第二数量与第一数量块相关联，第二数量小于第一数量。
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公开(公告)号：US10860323B2
公开(公告)日：2020-12-08
申请号：US15768254
申请日：2016-06-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiyoung Choi , Jun-whan Ahn , Sung-joo Yoo
IPC: G06F12/00 , G06F9/35 , G06F9/52 , G06F15/78 , G06F9/30 , G06F12/0811 , G06F12/0817 , G06F12/1027
Abstract: Provided is a method and apparatus for processing instructions using a processing-in-memory (PIM). A PIM management apparatus includes: a PIM directory comprising a reader-writer lock regarding a memory address that an instruction accesses; and a locality tracer configured to figure out locality regarding the memory address that the instruction accesses and determine whether or not an object that executes the instruction is a PIM.
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3.发明授权Semiconductor memory device including non-volatile memory, cache memory, and computer system 有权包括非易失性存储器，高速缓冲存储器和计算机系统的半导体存储器件公开(公告)号：US09250997B2
公开(公告)日：2016-02-02
申请号：US13790113
申请日：2013-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-gyeum Kim , Hyeok-man Kwon , Young-jun Kwon , Ki-young Choi , Jun-whan Ahn
CPC classification number: G06F11/1068 , G06F11/1064 , G11C11/1653 , G11C11/1677 , G11C29/52
Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.
Abstract translation: 在一个实施例中，存储器件包括数据存储区域和纠错（ECC）区域。 数据存储区域被配置为存储第一数量的数据块。 ECC区域被配置为存储第二数量的ECC块。 第二数量的ECC块中的每一个被配置为存储ECC信息。 ECC块的第二数量与第一数量块相关联，第二数量小于第一数量。
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