公开(公告)号：US20210263737A1

公开(公告)日：2021-08-26

申请号：US17007178

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyup LEE

IPC: G06F9/30 ,  G06F17/15 ,  H04L1/00 ,  G06T3/40

Abstract: A System-on-Chip (SoC) includes a first memory configured to store first data, a second memory, and a data processing circuit configured to divide the first data obtained from the first memory into a plurality of pieces of division data, assign a plurality of tags to the plurality of pieces of division data, each of the plurality of tags including a coordinate value for a corresponding piece of division data, obtain second data based on at least one of the first data and the plurality of tags for the plurality of pieces of division data, and provide an address and the second data to the second memory. The address and the second data are obtained based on the plurality of tags.

公开(公告)号：US20210312269A1

公开(公告)日：2021-10-07

申请号：US17223324

申请日：2021-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunpil KIM ,  Seongwoo AHN ,  Jonghyup LEE

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16 ,  G06F7/483 ,  G06N3/08

Abstract: A neural network device for performing a neural network operation includes a floating point arithmetic circuit configured to perform a dot-product operation for each of a plurality of floating point data pairs, wherein the floating point arithmetic circuit is configured to, in the dot-product operation, align-shift a plurality of fraction part multiplying operation results respectively corresponding to the floating point data pairs based on a maximum value determined from a plurality of exponent part adding operation results respectively corresponding to the floating point data pairs.