公开(公告)号：US10720470B2

公开(公告)日：2020-07-21

申请号：US16277385

申请日：2019-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongju Kim ,  Young-min Ko ,  Jong-uk Kim ,  Kwangmin Park ,  Jeong-hee Park

IPC: H01L27/24 ,  H01L45/00 ,  H01F10/32 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

Abstract: There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.

公开(公告)号：US20200052038A1

公开(公告)日：2020-02-13

申请号：US16277385

申请日：2019-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongju Kim ,  Young-min Ko ,  Jong-uk Kim ,  Kwangmin Park ,  Jeong-hee Park

IPC: H01L27/24 ,  H01L45/00

Abstract: There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.