公开(公告)号：US11545503B2

公开(公告)日：2023-01-03

申请号：US16747652

申请日：2020-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekyung Kim ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11519 ,  H01L29/792

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

公开(公告)号：US10541248B2

公开(公告)日：2020-01-21

申请号：US16045997

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekyung Kim ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

IPC: H01L23/528 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11519 ,  H01L29/792

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

公开(公告)号：US12029040B2

公开(公告)日：2024-07-02

申请号：US18083163

申请日：2022-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekyung Kim ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H10B41/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/35 ,  H01L29/4234 ,  H01L29/7926 ,  H10B41/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.