公开(公告)号：US20240145400A1

公开(公告)日：2024-05-02

申请号：US18227357

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhyuk Kim ,  Jeongyong Sung ,  Joongshik Shin ,  Jeehoon Han

IPC: H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H01L2223/54426

Abstract: A semiconductor device includes a substrate having first and second regions; a first stack structure including lower gate electrodes stacked in a first direction in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked in the first direction; a second channel structure penetrating through the second stack structure; a first mold structure including lower horizontal sacrificial layers stacked in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

公开(公告)号：US11728246B2

公开(公告)日：2023-08-15

申请号：US17331951

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Jinhyuk Kim ,  Jung-Hwan Kim

IPC: H01L29/78 ,  H01L23/48 ,  H01L25/065 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/481 ,  H01L25/0652 ,  H01L29/7827 ,  H10B41/27 ,  H10B43/27 ,  H01L2225/06541

Abstract: A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

公开(公告)号：US09431069B2

公开(公告)日：2016-08-30

申请号：US14299706

申请日：2014-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaesuk Lim ,  Jinhyuk Kim ,  Taekkyun Lee ,  Wonchuri Zoo

IPC: G06F11/00 ,  G11C5/14 ,  G11C29/44

CPC classification number: G11C5/148 ,  G11C2029/4402

Abstract: A management method for a memory system executes a first memory system management sequence upon determining that the memory system was normally powered off, and a second sequence upon determining that the memory system was abnormally powered off. The first sequence allows immediate execution of a program operation at a valid data page location extracted from stored metadata, while the second sequence allows execution of a program operation only after programming dummy data to at least one erroneous page.

Abstract translation: 存储系统的管理方法在确定存储器系统正常断电时执行第一存储器系统管理序列，并且在确定存储器系统异常断电时执行第二序列。 第一序列允许在从存储的元数据提取的有效数据页位置处立即执行程序操作，而第二序列仅允许在将伪数据编程到至少一个错误页面之后执行编程操作。

公开(公告)号：US20240107767A1

公开(公告)日：2024-03-28

申请号：US18463620

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Joonyoung Kwon ,  Jiyoung Kim ,  Jinhyuk Kim ,  Sukkang Sung

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A semiconductor device includes a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure includes gate electrodes stacked in a first direction and extending in a second direction. The first division pattern extends in the second direction through the gate electrode structure, and divides the gate electrode structure in a third direction. The memory channel structure extends through the gate electrode structure, and includes a channel and a charge storage structure. The first division pattern includes first and second sidewalls opposite to each other in the third direction. First recesses are spaced apart from each other in the second direction on the first sidewall, and second recesses are spaced apart from each other in the second direction on the second sidewall. The first and second recesses do not overlap in the third direction.

公开(公告)号：US11696447B2

公开(公告)日：2023-07-04

申请号：US17241232

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beyounghyun Koh ,  Seungmin Song ,  Joongshik Shin ,  Yongjin Kwon ,  Jinhyuk Kim ,  Hongik Son

IPC: H01L23/00 ,  H10B43/50 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/562 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

公开(公告)号：US20230422502A1

公开(公告)日：2023-12-28

申请号：US18202111

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seulji LEE ,  Jinhyuk Kim ,  Byoungil Lee ,  Sehoon Lee ,  Jinwoo Jeon

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes: a memory cell structure on a peripheral circuit structure; a through wiring region on the peripheral circuit structure; and a barrier structure surrounding the through wiring region. The memory cell structure includes: gate electrodes and first interlayer insulating layers that are alternately stacked, the gate electrodes forming a step shape on the second region; a channel structure; and isolation regions penetrating through the gate electrodes. The through wiring region includes: second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region; and a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices. Each of the sacrificial insulating layers includes a recess portion that is horizontally recessed from the barrier structure toward each of the sacrificial insulating layers.