公开(公告)号：US11183527B2

公开(公告)日：2021-11-23

申请号：US16410386

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Shi Li Quan ,  Hyung-yong Kim ,  Seug-gab Park ,  In-gyu Baek ,  Kyung-rae Byun ,  Jin-yong Choi

IPC: H01L27/146 ,  H04N5/335

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

公开(公告)号：US11508775B2

公开(公告)日：2022-11-22

申请号：US17398493

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Shi Li Quan ,  Hyung-yong Kim ,  Seug-gab Park ,  In-gyu Baek ,  Kyung-rae Byun ,  Jin-yong Choi

IPC: H01L27/146 ,  H04N5/335

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

公开(公告)号：US10510429B2

公开(公告)日：2019-12-17

申请号：US16007528

申请日：2018-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-yong Choi ,  Kyung-ryun Kim ,  Woong-dai Kang ,  Hyun-chul Yoon

IPC: G11C29/04 ,  G11C29/24 ,  G11C29/12 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.