公开(公告)号：US20180174959A1

公开(公告)日：2018-06-21

申请号：US15677054

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ju KIM ,  Su-A KIM ,  Soo-Young KIM ,  Min-Woo WON ,  Bok-Yeon WON ,  Ji-Suk KWON ,  Young-Ho KIM ,  Ji-Hak YU ,  Hyun-Chul YOON ,  Seok-Jae LEE ,  Sang-Keun HAN ,  Woong-Dai KANG ,  Hyuk-Joon KWON ,  Bum-Jae LEE

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/552 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5225 ,  G11C7/06 ,  G11C7/1057 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/06 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/06155 ,  H01L2224/06159 ,  H01L2224/12105 ,  H01L2924/18162 ,  H01L2924/3025

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

公开(公告)号：US20240402248A1

公开(公告)日：2024-12-05

申请号：US18632845

申请日：2024-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dojong CHUN ,  Jungwook KIM ,  Minsu PARK ,  Ji-Suk KWON ,  Seokjae LEE

IPC: G01R31/317 ,  H01L21/66

Abstract: Disclosed is a memory device. The memory device includes a memory cell array; a first pad configured to receive a command from an external device; a second pad configured to exchange data with the external device; a third pad; test logic configured to generate a test pulse signal based on a test command received through the first pad; and a crack detection structure formed below the third pad and configured to include lines connected in series from the test logic to the second pad. A crack occurring in the third pad is detected based on a delay of a delay pulse signal changed when the test pulse signal passes through the crack detection structure.