公开(公告)号：US12107049B2

公开(公告)日：2024-10-01

申请号：US17481609

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younseok Choi ,  Byungsun Park ,  Youngil Lee ,  Jaechul Lee ,  Jiwoon Im

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/5329 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a lower memory stack disposed on a substrate and including lower gate electrodes and a lower staircase structure, an upper memory stack including upper gate electrodes and an upper staircase structure, a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure, an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer, lower contact plugs and upper contact plugs contacting the lower gate electrodes and the upper gate electrodes, respectively.

公开(公告)号：US20230262980A1

公开(公告)日：2023-08-17

申请号：US17936473

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjae Sim ,  Byung-Sun Park ,  Jaechul Lee ,  Dae-Hun Choi

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device, a method of fabricating the same, and an electronic system including the same. The semiconductor memory device may include a substrate including a first region and a second region, a plurality of stacks including first and second stacks, each of which includes interlayer insulating layers and gate electrodes stacked alternately with the interlayer insulating layers on the substrate and has a stepped structure on the second region, an insulating layer on stepped structure of the first stack, a plurality of vertical channel structures provided on the first region to penetrate the first stack, and a separation structure separating the first and second stacks from each other. The insulating layer may include one or more dopants, and a dopant concentration of the insulating layer may decrease as a distance from the substrate increases.