公开(公告)号：US20180322083A1

公开(公告)日：2018-11-08

申请号：US16034470

申请日：2018-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl KIM ,  Chih Jen LIM ,  Jinook SONG ,  Sungjae LEE ,  Hyun-ki KOO ,  Donghyeon HAM

IPC: G06F13/40 ,  G06T1/20 ,  G06F13/16

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

公开(公告)号：US20180276052A1

公开(公告)日：2018-09-27

申请号：US15670370

申请日：2017-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl KIM ,  Yun-Gwan YU

IPC: G06F9/52 ,  G06F11/30 ,  G06F11/36

CPC classification number: G06F9/524 ,  G06F11/22 ,  G06F11/3089 ,  G06F11/362 ,  G06F11/3648 ,  G06F13/36

Abstract: A system includes a plurality of hardware blocks, a deadlock detector and an interconnect device. The hardware blocks include a processor executing instructions and a storage device storing data. The deadlock detector monitors operations of a target hardware block among the plurality of hardware blocks in realtime to store debugging information in the storage device. The interconnect device electrically connects the deadlock detector and the plurality of hardware blocks. The interconnect device includes a system bus electrically connecting the plurality of hardware blocks and a debugging bus electrically connecting the deadlock detector to the target hardware block and the storage device. The interconnect device includes a system bus electrically connecting the plurality of hardware blocks and a debugging bus electrically connecting the deadlock detector to the target hardware block and the storage device.

公开(公告)号：US20170199835A1

公开(公告)日：2017-07-13

申请号：US14995179

申请日：2016-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl KIM ,  Chih Jen LIN ,  Jinook SONG ,  Sungjae LEE ,  Hyun-ki KOO ,  Donghyeon HAM

IPC: G06F13/40 ,  G06T1/20 ,  G06F13/16

CPC classification number: G06F13/4036 ,  G06F13/1605 ,  G06F2213/16 ,  G06F2213/36 ,  G06T1/20 ,  G06T2200/28

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC includes a processor of the SoC including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus, the deadlock controller being configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and extract, via the second bus, state information of the isolated processor in the deadlock state.