公开(公告)号：US20240237333A9

公开(公告)日：2024-07-11

申请号：US18220861

申请日：2023-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jul Pin PARK ,  Jae Joon SONG ,  Heon Jun HA ,  Dong-Sik PARK

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/482 ,  H01L23/5283 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: Disclosed is a semiconductor memory device including a peripheral gate structure on a substrate, bitlines disposed on the peripheral gate structure and extending in a first direction, a protruding insulating pattern including channel trenches, extending in a second direction intersecting the first direction, channel structures disposed on the bitlines in the channel trenches and including a metal oxide, first wordlines disposed on the channel structures and extending in the second direction, second wordlines disposed on the channel structures, extending in the second direction, and spaced apart from the first wordlines in the first direction, landing pads disposed on the channel structures and connected to the channel structures, pad separation patterns disposed on the protruding insulating pattern and separating the landing pads, first passage patterns connected to the protruding insulating pattern through pad separation patterns and formed of an oxide-based insulating material, and data storage patterns disposed on the landing pads.

公开(公告)号：US20180122810A1

公开(公告)日：2018-05-03

申请号：US15621315

申请日：2017-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon HAN ,  Dong Wan KIM ,  Ji Hun KIM ,  Jae Joon SONG ,  Hiroshi TAKEDA

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/90

Abstract: A semiconductor device is provided. The semiconductor device includes an upper interlayer insulating layer disposed on a substrate. A first electrode spaced apart from the upper interlayer insulating layer is disposed on the substrate. A contact structure penetrating the upper interlayer insulating layer is disposed on the substrate. An upper support layer having a first portion covering an upper surface of the upper interlayer insulating layer, to surround an upper side surface of the contact structure, and a second portion extending in a horizontal direction from the first portion and surrounding an upper side surface of the first electrode, is disposed. A dielectric conformally covering the first electrode and a second electrode on the dielectric are disposed.

公开(公告)号：US20240138142A1

公开(公告)日：2024-04-25

申请号：US18220861

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jul Pin PARK ,  Jae Joon SONG ,  Heon Jun HA ,  Dong-Sik PARK

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/482 ,  H01L23/5283 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: Disclosed is a semiconductor memory device including a peripheral gate structure on a substrate, bitlines disposed on the peripheral gate structure and extending in a first direction, a protruding insulating pattern including channel trenches, extending in a second direction intersecting the first direction, channel structures disposed on the bitlines in the channel trenches and including a metal oxide, first wordlines disposed on the channel structures and extending in the second direction, second wordlines disposed on the channel structures, extending in the second direction, and spaced apart from the first wordlines in the first direction, landing pads disposed on the channel structures and connected to the channel structures, pad separation patterns disposed on the protruding insulating pattern and separating the landing pads, first passage patterns connected to the protruding insulating pattern through pad separation patterns and formed of an oxide-based insulating material, and data storage patterns disposed on the landing pads.

公开(公告)号：US20180145080A1

公开(公告)日：2018-05-24

申请号：US15644877

申请日：2017-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Wan KIM ,  Ji Hun KIM ,  Jae Joon SONG ,  Hiroshi TAKEDA ,  Jung Hoon HAN

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L23/528 ,  H01L21/28

CPC classification number: H01L27/10823 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/7682 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/66621

Abstract: A semiconductor device including a substrate; a trench formed within the substrate; a gate insulating film formed conformally along a portion of a surface of the trench; a gate electrode formed on the gate insulating film and filling a portion of the trench; a capping film formed on the gate electrode and filling the trench; and an air gap formed between the capping film and the gate insulating film.