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公开(公告)号：US20220278475A1
公开(公告)日：2022-09-01
申请号：US17743197
申请日：2022-05-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seon Gyun BAEK , Jae Hong PARK , Yusuf CINAR , Han Hong LEE
IPC: H01R13/50 , H01R13/6585 , H01R13/6581 , H01R13/405
Abstract: Provided are a receptacle connector configured to avoid damage to conductors of the receptacle connector. The receptacle connector includes a plurality of connection terminals, a mold structure which comprises a front part exposing each of the connection terminals and a support part disposed on a rear end of the front part and surrounding each of the connection terminals, and a shield which is disposed on the support part and comprises a conductive material, wherein the support part comprises a flat part which includes a surface along which the shield extends and a protruding part which protrudes from the surface of the flat part and is disposed in front of a front end of the shield. The protruding part is configured to avoid damage to conductors of the receptacle when a plug is mated to the receptacle.
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公开(公告)号：US20220102358A1
公开(公告)日：2022-03-31
申请号：US17461051
申请日：2021-08-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hong PARK , Jae-Wha PARK , Moon Keun KIM , Jung Ha HWANG
IPC: H01L27/108
Abstract: A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.
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公开(公告)号：US20240114638A1
公开(公告)日：2024-04-04
申请号：US18529889
申请日：2023-12-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yusuf CINAR , Jae Hong PARK , Han Hong LEE , Seon Gyun BAEK , Won-Gi HONG
CPC classification number: H05K5/0217 , H01R12/7023 , H01R12/721 , H01R12/73 , H01R13/621 , H05K5/0008 , H05K5/026 , H05K7/20409 , H01L25/18
Abstract: A memory device and an electronic device is provided. The memory device may include a memory module including a module board and a memory connector located on one side of the module board, a first enclosure placed above the memory module and a second enclosure placed below the memory module, wherein the first enclosure includes a first main cover which covers upper faces of the module board and the memory connector, at least one clamping hole which penetrates the main cover at a position overlapping the memory connector, an inter-device fastening pillar protruding downward from a lower face of the first main cover, and a coupling hole which is located inside the inter-device fastening pillar on a plane and penetrates the inter-device fastening pillar and the main cover.
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公开(公告)号：US20240292608A1
公开(公告)日：2024-08-29
申请号：US18659188
申请日：2024-05-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hong PARK , Jae-Wha PARK , Moon Keun KIM , Jung Ha HWANG
Abstract: A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.
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Patent Agency Ranking
公开(公告)号：US20210006001A1
公开(公告)日：2021-01-07
申请号：US16822872
申请日：2020-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seon Gyun BAEK , Jae Hong PARK , Yusuf CINAR , Han Hong LEE
IPC: H01R13/50 , H01R13/405 , H01R13/6581 , H01R13/6585
Abstract: Provided are a receptacle connector configured to avoid damage to conductors of the receptacle connector. The receptacle connector includes a plurality of connection terminals, a mold structure which comprises a front part exposing each of the connection terminals and a support part disposed on a rear end of the front part and surrounding each of the connection terminals, and a shield which is disposed on the support part and comprises a conductive material, wherein the support part comprises a flat part which includes a surface along which the shield extends and a protruding part which protrudes from the surface of the flat part and is disposed in front of a front end of the shield. The protruding part is configured to avoid damage to conductors of the receptacle when a plug is mated to the receptacle.
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公开(公告)号：US20190273130A1
公开(公告)日：2019-09-05
申请号：US16419153
申请日：2019-05-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jun Ho YOON , Won Chul LEE , Sung Yeon KIM , Jae Hong PARK , Chan Hoon PARK , Yong Moon JANG , Je Woo HAN
IPC: H01L49/02 , H01L21/283 , H01L21/033 , H01L21/311
Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
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公开(公告)号：US20180108728A1
公开(公告)日：2018-04-19
申请号：US15626271
申请日：2017-06-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jun Ho YOON , Won Chul LEE , Sung Yeon KIM , Jae Hong PARK , Chan Hoon PARK , Yong Moon JANG , Je Woo HAN
IPC: H01L49/02 , H01L21/311 , H01L21/283
CPC classification number: H01L28/60 , H01L21/283 , H01L21/31105 , H01L21/31116 , H01L21/31144
Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
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公开(公告)号：US20210385956A1
公开(公告)日：2021-12-09
申请号：US17217759
申请日：2021-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yusuf CINAR , Jae Hong PARK , Han Hong LEE , Seon Gyun BAEK , Won-Gi HONG
Abstract: A memory device and an electronic device is provided. The memory device may include a memory module including a module board and a memory connector located on one side of the module board, a first enclosure placed above the memory module and a second enclosure placed below the memory module, wherein the first enclosure includes a first main cover which covers upper faces of the module board and the memory connector, at least one clamping hole which penetrates the main cover at a position overlapping the memory connector, an inter-device fastening pillar protruding downward from a lower face of the first main cover, and a coupling hole which is located inside the inter-device fastening pillar on a plane and penetrates the inter-device fastening pillar and the main cover.
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公开(公告)号：US20190304895A1
公开(公告)日：2019-10-03
申请号：US16181739
申请日：2018-11-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hong PARK , Woo Jin LEE
IPC: H01L23/522 , H01L21/311 , H01L21/768 , H01L23/532
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate, a first metal wiring and a second metal wiring disposed in the interlayer insulating layer, the first and second wirings spaced apart from each other in a first direction, the first and second wirings extending to a second direction perpendicular to the first direction, an air gap formed in the interlayer insulating layer between the first metal wiring and the second metal wiring, and spaced apart from a sidewall of the first metal wiring and a sidewall of the second metal wiring, and a capping layer disposed on the interlayer insulating layer, the capping layer covering the first metal wiring, the second metal wiring, and the air gap, wherein the air gap is disposed at a first distance from the first metal wiring in the first direction and at a second distance from the second metal wiring in the first direction, and wherein the first and second distances are the same.
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