公开(公告)号：US20220115281A1

公开(公告)日：2022-04-14

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  DONGHO KIM ,  JIN-WOO PARK ,  JONGBO SHIM

IPC: H01L23/13 ,  H01L25/10 ,  H01L21/48 ,  H01L25/00

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate. wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

公开(公告)号：US20240120251A1

公开(公告)日：2024-04-11

申请号：US18213851

申请日：2023-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIN-WOO PARK ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/92125 ,  H10B80/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a base semiconductor chip, a chip structure on the base semiconductor chip, a connection terminal between the base semiconductor chip and the chip structure, and a molding layer surrounding the chip structure and the connection terminal. The chip structure includes a first semiconductor chip including a first frontside pad and a first backside pad, and a second semiconductor including a second frontside pad and a second backside pad. A lateral surface of the first semiconductor chip is aligned with that of the second semiconductor chip. The first backside pad and the second frontside pad partially overlap each other when viewed in plan while being in direct contact with each other. The first backside pad and the second frontside pad include the same metal and are formed into a single unitary piece.

公开(公告)号：US20230402358A1

公开(公告)日：2023-12-14

申请号：US18174992

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHOONGBIN YIM ,  JI-YONG PARK ,  JIN-WOO PARK

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/3107 ,  H01L24/24 ,  H01L2224/24225 ,  H01L2224/19 ,  H01L24/19 ,  H01L2224/24011 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, substrate pads provided on a top surface of the package substrate, at least one core ball on at least one of the substrate pads, a redistribution substrate provided on the top surface of the package substrate, and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate is electrically connected to the package substrate through a plurality of solder balls provided on a bottom surface of the redistribution substrate. The at least one core ball is electrically connected to the redistribution substrate. A diameter of the at least one core ball is greater than a diameter of each of the plurality of solder balls.

公开(公告)号：US20160351155A1

公开(公告)日：2016-12-01

申请号：US15165464

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-WOO PARK ,  SO-YOUNG LIM

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G2300/0426 ,  G09G2330/021

Abstract: A chip on film (COF) package includes a base film, a semiconductor chip disposed on the base film, first signal wires, and second signal wires. The semiconductor chip includes a pads and a driving integrated circuit. The first signal wires are configured to output a drive signal generated in the driving integrated circuit, and are electrically connected to pads disposed in a first pad region. The first pad region is disposed on a first side of the semiconductor chip. The first signal wires are disposed on a first surface of the base film. The second signal wires are electrically connected to pads disposed in a second pad region. The second pad region is disposed on a second side of the semiconductor chip. The second signal wires are disposed on a second surface of the base film. The first and second surfaces of the base film are opposite to each other.

Abstract translation: 膜芯片（COF）封装包括基膜，设置在基膜上的半导体芯片，第一信号线和第二信号线。 半导体芯片包括焊盘和驱动集成电路。 第一信号线被配置为输出在驱动集成电路中产生的驱动信号，并且电连接到设置在第一焊盘区域中的焊盘。 第一焊盘区域设置在半导体芯片的第一侧上。 第一信号线设置在基膜的第一表面上。 第二信号线电连接到设置在第二焊盘区域中的焊盘。 第二焊盘区域设置在半导体芯片的第二侧上。 第二信号线设置在基膜的第二表面上。 基膜的第一和第二表面彼此相对。

公开(公告)号：US20240222331A1

公开(公告)日：2024-07-04

申请号：US18473126

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-WOO PARK ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/0903 ,  H01L2224/09152 ,  H01L2224/16014 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/3511

Abstract: A semiconductor package includes a buffer chip configured to include a first dummy region and a second dummy region and to include first pads on rear surfaces of substrates of the first and second dummy regions; and a first core chip stacked at an upper portion of the buffer to include a bump 116 coupled to the first pad and positioned on an entire surface of the substrate, wherein the first pad is positioned in a line shape having a length including at least two bumps.