公开(公告)号：US20160141015A1

公开(公告)日：2016-05-19

申请号：US14837294

申请日：2015-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Hun LEE ,  Hyung-Chan CHOI ,  Won-Jae SHIN

IPC: G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4074 ,  G11C5/145 ,  G11C5/148 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4087

Abstract: A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level.

Abstract translation: 存储器件可以包括上电控制电路和第一组升压电压发生器。 上电控制电路可以被配置为响应于电源电压的上升，以第一组加电信号的每个上电信号之间的第一延迟时间连续激活第一组上电信号 以及在上电初始阶段具有第一逻辑电平的复位信号。 第一组升压电压发生器可以被配置为基于外部升压电压和第一组上电信号产生内部升压电压。 第一组升压电压发生器可以被配置为在复位信号从第一逻辑电平转变到与第一逻辑电平相反的第二逻辑电平之前激活。