公开(公告)号：US20230200039A1

公开(公告)日：2023-06-22

申请号：US17865065

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonsung CHOI ,  Minuk LEE

IPC: H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412

Abstract: The present disclosure refers to integrated circuits and static random access memories. In an embodiment, an integrated circuit includes a first n-type metal oxide semiconductor (NMOS) region, a second NMOS region, a first p-type MOS (PMOS) region between the first NMOS region and the second NMOS region, a second PMOS region between the first PMOS region and the second NMOS region, and a first active bridge extending in a first direction and coupling the first NMOS region to the first PMOS region. A level of the first active bridge matches levels of the first electrode of the first pass transistor, the second electrode of the first pass transistor, the first electrode of the first pull-down transistor, the second electrode of the first pull-down transistor, the first electrode of the first pull-up transistor, and the second electrode of the first pull-up transistor.

公开(公告)号：US20250040133A1

公开(公告)日：2025-01-30

申请号：US18913478

申请日：2024-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonsung CHOI ,  Jiyoung YUN

IPC: H10B20/25

Abstract: A semiconductor integrated circuit device includes a standard cell on a substrate, an one time programmable (OTP) memory structure at an edge portion of the standard cell, and a program transistor outside of the standard cell at a position adjacent to the edge portion of the standard cell at which the OTP memory structure is provided, the program transistor being electrically connected to the OTP memory structure. The OTP memory structure includes a first anti-fuse and a second anti-fuse. When a program voltage is applied to the program transistor and a bias power voltage is applied to the OTP memory structure, each of the first anti-fuse and the second anti-fuse becomes shorted and the bias power voltage is provided to the standard cell.

公开(公告)号：US20230096886A1

公开(公告)日：2023-03-30

申请号：US17740635

申请日：2022-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonsung CHOI ,  Jiyoung YUN

IPC: H01L27/112

Abstract: A semiconductor integrated circuit device includes a standard cell on a substrate, an one time programmable (OTP) memory structure at an edge portion of the standard cell, and a program transistor outside of the standard cell at a position adjacent to the edge portion of the standard cell at which the OTP memory structure is provided, the program transistor being electrically connected to the OTP memory structure. The OTP memory structure includes a first anti-fuse and a second anti-fuse. When a program voltage is applied to the program transistor and a bias power voltage is applied to the OTP memory structure, each of the first anti-fuse and the second anti-fuse becomes shorted and the bias power voltage is provided to the standard cell.

公开(公告)号：US20230402463A1

公开(公告)日：2023-12-14

申请号：US18108125

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonsung CHOI ,  Youngmok Kim ,  Sangjin Lee

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L21/823462

Abstract: A semiconductor device includes a bulk substrate including a first region and a second region, a buried oxide layer and a semiconductor layer stacked on the first region, a first gate structure disposed on the semiconductor layer, a first source/drain layer disposed at an upper portion of the semiconductor layer adjacent to the first gate structure, a second gate structure disposed on the second region, and a second source/drain layer disposed at an upper portion of the bulk substrate adjacent to the second gate structure.

公开(公告)号：US20220375948A1

公开(公告)日：2022-11-24

申请号：US17558884

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonsung CHOI ,  Jinwoo PARK

IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  G11C17/14

Abstract: A one-time programmable (OTP) memory device includes an access transistor, a word line, a voltage line, a well, a first filling oxide layer, a first semiconductor layer, and a bit line. The access transistor includes a gate structure on a substrate, and first and second impurity regions at portions of the substrate adjacent to the gate structure. The word line is electrically connected to the gate structure. The voltage line is electrically connected to the first impurity region. The well is formed at an upper portion of the substrate, and is doped with impurities having a first conductivity type. The first filling oxide layer is formed on the well. The first semiconductor layer is formed on the first filling oxide layer, and is doped with impurities having the first conductivity type and electrically connected to the second impurity region. The bit line is electrically connected to the well.