公开(公告)号：US11436081B2

公开(公告)日：2022-09-06

申请号：US17018763

申请日：2020-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeul Na ,  Jaehun Jang ,  Hongrak Son

IPC: G06F11/10 ,  G06F11/07

Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.

公开(公告)号：US12019871B2

公开(公告)日：2024-06-25

申请号：US17865621

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsuk Ra ,  Hanbyeul Na ,  Kwanwoo Noh ,  Mankeun Seo ,  Hong Rak Son ,  Jae Hun Jang

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.

公开(公告)号：US11797381B2

公开(公告)日：2023-10-24

申请号：US17816554

申请日：2022-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeul Na ,  Jaehun Jang ,  Hongrak Son

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1044

Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.

公开(公告)号：US12231531B2

公开(公告)日：2025-02-18

申请号：US17739512

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsik Moon ,  Jiyoup Kim ,  Hanbyeul Na ,  Hongrak Son

IPC: H04L9/00 ,  G06F21/60 ,  H04L9/06 ,  H04L9/30

Abstract: A homomorphic encryption system includes a homomorphic encryption device encrypting original data into a first ciphertext using a homomorphic encryption algorithm, and a homomorphic encryption operation device receiving the first ciphertext from the homomorphic encryption device and performing an approximate arithmetic operation of a transcendental function with respect to the first ciphertext and a second ciphertext by performing a homomorphic multiplication operation in a binary tree structure.

公开(公告)号：US12184755B2

公开(公告)日：2024-12-31

申请号：US17739512

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsik Moon ,  Jiyoup Kim ,  Hanbyeul Na ,  Hongrak Son

IPC: H04L9/00 ,  G06F21/60 ,  H04L9/06 ,  H04L9/30

Abstract: A homomorphic encryption system includes a homomorphic encryption device encrypting original data into a first ciphertext using a homomorphic encryption algorithm, and a homomorphic encryption operation device receiving the first ciphertext from the homomorphic encryption device and performing an approximate arithmetic operation of a transcendental function with respect to the first ciphertext and a second ciphertext by performing a homomorphic multiplication operation in a binary tree structure.

公开(公告)号：US11539504B2

公开(公告)日：2022-12-27

申请号：US17336625

申请日：2021-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeul Na ,  Sumin Kim ,  Hongrak Son ,  Junho Shin

IPC: H04L9/00 ,  H04L9/30 ,  H04L9/08 ,  G06F7/46

Abstract: A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive cipher text data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the cipher text data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the cipher text data.