公开(公告)号：US20250021122A1

公开(公告)日：2025-01-16

申请号：US18412844

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haejung CHOI ,  Jooseong KIM ,  Junhyeok YANG ,  Sungmin YOO

IPC: G05F3/20 ,  G05F1/567 ,  G05F3/26

Abstract: A semiconductor device including a bandgap reference generator that generates a reference voltage; a switch control voltage generator that generates a first reference current based on the reference voltage, and generates an adaptive switch level voltage by distributing the first reference current to a first path and a second path, the first path including a first resistor, and the second path including a second resistor and a first bipolar junction transistor connected in series; and a switch controller that generates a switch control signal for controlling switches included in the bandgap reference generator based on the adaptive switch level voltage. The adaptive switch level voltage has a slope with respect to temperature that is greater than a base-emitter voltage of the first bipolar junction transistor.

公开(公告)号：US20240183901A1

公开(公告)日：2024-06-06

申请号：US18523269

申请日：2023-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haejung CHOI ,  Youngbin Kwon ,  Donghun Heo

IPC: G01R31/317 ,  G06F1/08 ,  H03K21/08

CPC classification number: G01R31/31727 ,  G06F1/08 ,  H03K21/08

Abstract: A clock monitoring circuit includes a clock enable signal generator configured to generate an ultra-high frequency clock enable signal based on a clock enable control signal and a reference clock signal, and an ultra-high frequency detector configured to generate an ultra-high frequency determination signal indicating whether a selection clock signal is an ultra-high frequency signal, based on the selection clock signal, the ultra-high frequency clock enable signal, and the reference clock signal.

公开(公告)号：US20230020463A1

公开(公告)日：2023-01-19

申请号：US17860699

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheolhwan LIM ,  Kwangho KIM ,  Sangjin LIM ,  Haejung CHOI ,  Donghun HEO

IPC: H01L23/00 ,  G01J1/42

Abstract: A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

公开(公告)号：US20220357372A1

公开(公告)日：2022-11-10

申请号：US17872363

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolhwan LIM ,  Junhee SHIN ,  Haejung CHOI ,  Kwangho KIM ,  Hyunmyoung KIM

IPC: G01R19/165 ,  H03K17/687 ,  H03K3/037 ,  G06F1/24 ,  G06F1/28

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

公开(公告)号：US20210239744A1

公开(公告)日：2021-08-05

申请号：US17036394

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolhwan LIM ,  Junhee SHIN ,  Haejung CHOI ,  Kwangho KIM ,  Hyunmyoung KIM

IPC: G01R19/165 ,  H03K3/037 ,  H03K17/687

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.