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公开(公告)号:US20230020463A1
公开(公告)日:2023-01-19
申请号:US17860699
申请日:2022-07-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Cheolhwan LIM , Kwangho KIM , Sangjin LIM , Haejung CHOI , Donghun HEO
Abstract: A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.
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公开(公告)号:US20220357372A1
公开(公告)日:2022-11-10
申请号:US17872363
申请日:2022-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Cheolhwan LIM , Junhee SHIN , Haejung CHOI , Kwangho KIM , Hyunmyoung KIM
IPC: G01R19/165 , H03K17/687 , H03K3/037 , G06F1/24 , G06F1/28
Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.
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公开(公告)号:US20210239744A1
公开(公告)日:2021-08-05
申请号:US17036394
申请日:2020-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Cheolhwan LIM , Junhee SHIN , Haejung CHOI , Kwangho KIM , Hyunmyoung KIM
IPC: G01R19/165 , H03K3/037 , H03K17/687
Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.
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