公开(公告)号：US20160099185A1

公开(公告)日：2016-04-07

申请号：US14854528

申请日：2015-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chongkwang Chang ,  Sungwoo Kang ,  Chunghowan Kim ,  Youngmook Oh ,  Seobum Lee ,  Gahyun Lim

IPC: H01L21/66 ,  H01L21/308

CPC classification number: H01L22/20 ,  H01L21/3085 ,  H01L22/12 ,  H01L27/1104

Abstract: A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.

Abstract translation: 一种控制用于形成半导体器件精细图案的蚀刻工艺的方法包括在衬底上形成具有多个开口的下部图案，获得下部图案的宽度值，以及控制用于形成 使用宽度值降低图案。

公开(公告)号：US09397013B2

公开(公告)日：2016-07-19

申请号：US14854528

申请日：2015-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chongkwang Chang ,  Sungwoo Kang ,  Chunghowan Kim ,  Youngmook Oh ,  Seobum Lee ,  Gahyun Lim

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/308

CPC classification number: H01L22/20 ,  H01L21/3085 ,  H01L22/12 ,  H01L27/1104

Abstract: A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.

Abstract translation: 一种控制用于形成半导体器件精细图案的蚀刻工艺的方法包括在衬底上形成具有多个开口的下部图案，获得下部图案的宽度值，以及控制用于形成 使用宽度值降低图案。