公开(公告)号：US20210130651A1

公开(公告)日：2021-05-06

申请号：US16912426

申请日：2020-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNSUNG SEO ,  CHANG GIL KWON ,  SUNG PYO LEE ,  DONGCHAN KIM ,  BO YUN KIM ,  JUN HA HWANG

IPC: C09G1/18 ,  H01L21/321

Abstract: Described herein are chemical mechanical polishing (CMP) slurry compositions, such as CMP slurry compositions for polishing an indium tin oxide (ITO) layer, along with methods of fabricating a semiconductor device using such a CMP slurry composition. The CMP slurry composition can include a polishing particle, a dispersing agent, an auxiliary oxidizing agent, and a sugar alcohol compound.

公开(公告)号：US20150228327A1

公开(公告)日：2015-08-13

申请号：US14692797

申请日：2015-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNSUNG SEO ,  CHUL-SUNG PARK ,  CHI-SUNG OH

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C17/16

CPC classification number: G11C11/4076 ,  G11C7/10 ,  G11C11/4093 ,  G11C17/16 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/22

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract translation: 存储器装置包括共享输入/输出线的至少两个存储器等级，至少一个模式寄存器，被配置为存储用于调整通过输入/输出线输出的至少两个等级的数据信号延迟的位;控制器，被配置为确定 基于所述至少一个模式寄存器中存储的比特来调整所述数据信号的参数，所述调整参数至少包括所述数据信号的延迟，以及至少一个非易失性存储器，其被布置在所述至少两个存储器排中的至少一个中 并且被配置为存储调谐参数。

公开(公告)号：US20140078840A1

公开(公告)日：2014-03-20

申请号：US13967506

申请日：2013-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNSUNG SEO ,  CHUL-SUNG PARK ,  CHI-SUNG OH

IPC: G11C7/10

CPC classification number: G11C11/4076 ,  G11C7/10 ,  G11C11/4093 ,  G11C17/16 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/22

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract translation: 存储器装置包括共享输入/输出线的至少两个存储器等级，至少一个模式寄存器，被配置为存储用于调整通过输入/输出线输出的至少两个等级的数据信号延迟的位;控制器，被配置为确定 基于所述至少一个模式寄存器中存储的比特来调整所述数据信号的参数，所述调整参数至少包括所述数据信号的延迟，以及至少一个非易失性存储器，其被布置在所述至少两个存储器排中的至少一个中 并且被配置为存储调谐参数。