公开(公告)号：US20240179917A1

公开(公告)日：2024-05-30

申请号：US18360128

申请日：2023-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minji PARK ,  Dongha SHIN ,  Hongsoo JEON

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35

Abstract: Disclosed are semiconductor memory devices comprising a peripheral region including a substrate, high voltage transistors on the substrate, first lower lines connected to the high voltage transistors, and second lower lines connected to the first lower lines, and a cell region on the peripheral region. The first and the second lower lines extend along a first direction parallel to an upper surface of the substrate. The first lower lines include first high voltage lines and first low voltage lines. The second lower lines include second high voltage lines and second low voltage lines. The second high voltage lines and the first low voltage lines separated in a second direction parallel to the upper surface of the substrate and a third direction perpendicular to the upper surface of the substrate, and the second low voltage lines and the first high voltage lines separated in the second direction and the third direction.

公开(公告)号：US20240130131A1

公开(公告)日：2024-04-18

申请号：US18301575

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeawon JEONG ,  Dongha SHIN ,  Bongsoon LIM

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device may include word line patterns stacked on a substrate and spaced from each other in a vertical direction, a channel structure extending in the vertical direction, and first contact plugs and second contact plugs extending in the vertical direction. The substrate may include a cell area, a cell wiring area, and a through-hole wiring area. The word line patterns may be on the cell area and the cell wiring area and may extend to the cell wiring area in a direction parallel to an upper surface of the substrate. The first contact plugs may be on the cell wiring area and each may be electrically connected with a corresponding one of the word line patterns and insulated from remaining word line patterns other than the corresponding one of the word line patterns. The second contact plugs may be on the through-hole wiring area.

公开(公告)号：US20210366825A1

公开(公告)日：2021-11-25

申请号：US17212222

申请日：2021-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongha SHIN ,  Jeawon JEONG ,  Bongsoon LIM

IPC: H01L23/522 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts.