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公开(公告)号:US09893721B2
公开(公告)日:2018-02-13
申请号:US15206384
申请日:2016-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Seok Lee , Woo-Seok Kim , Jae-Jin Park , Dong-Hyuk Lim , Dae-Young Chung
IPC: H03K5/1534 , H04L7/00 , H03K19/21 , H01L27/118
CPC classification number: H03K5/1534 , G01R31/00 , H01L27/11803 , H01L28/00 , H01L2027/11881 , H03K19/21 , H04L1/00 , H04L7/0037 , H04L7/0087
Abstract: An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.
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公开(公告)号:USD725656S1
公开(公告)日:2015-03-31
申请号:US29468839
申请日:2013-10-03
Applicant: Samsung Electronics Co., Ltd.
Designer: Dong-Seok Lee , Sang-Won Yoon
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公开(公告)号:USD705214S1
公开(公告)日:2014-05-20
申请号:US29440638
申请日:2012-12-24
Applicant: Samsung Electronics Co., Ltd.
Designer: Dong-Seok Lee , Son-Young Lee
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公开(公告)号:US20160155669A1
公开(公告)日:2016-06-02
申请号:US14555775
申请日:2014-11-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Seok Lee , Kang-III SEO
IPC: H01L21/8234 , H01L21/306 , H01L21/311 , H01L21/3065 , H01L21/308 , H01L21/762
CPC classification number: H01L21/823431 , H01L21/3083 , H01L21/845 , H01L29/66795
Abstract: An exemplary method of fabricating a semiconductor device is provided. First and second hard mask patterns adjacent to each other are formed on a substrate. First and second active fins are formed by etching the substrate using the first and second hard mask patterns as a etch mask. An isolation layer is formed to fill a region defined by the first and second active fins and the first and second hard mask patterns. A mask pattern is formed to be positioned on the first hard mask pattern and overlap the first active fin. A first trench is formed by etching a portion of the isolation layer and a portion of the second active fin using the mask pattern as an etch mask. The remaining portion of the second active fin is removed by performing an isotropic etching process.
Abstract translation: 提供了一种制造半导体器件的示例性方法。 在基板上形成彼此相邻的第一和第二硬掩模图案。 通过使用第一和第二硬掩模图案作为蚀刻掩模蚀刻衬底来形成第一和第二活性鳍。 形成隔离层以填充由第一和第二活动鳍片以及第一和第二硬掩模图案限定的区域。 形成掩模图案以定位在第一硬掩模图案上并且与第一活动散热片重叠。 通过使用掩模图案作为蚀刻掩模蚀刻隔离层的一部分和第二有源散热片的一部分来形成第一沟槽。 通过执行各向同性蚀刻工艺来去除第二活性鳍片的剩余部分。
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公开(公告)号:USD740289S1
公开(公告)日:2015-10-06
申请号:US29469154
申请日:2013-10-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Felix Heck , Sang-Won Yoon , Yeo-Wan Yun , Dong-Seok Lee
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公开(公告)号:USD716793S1
公开(公告)日:2014-11-04
申请号:US29453620
申请日:2013-05-01
Applicant: Samsung Electronics Co., Ltd.
Designer: Dong-Seok Lee , Ik-Sang Kim , Sang-Won Yoon
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公开(公告)号:USD715792S1
公开(公告)日:2014-10-21
申请号:US29469157
申请日:2013-10-08
Applicant: Samsung Electronics Co., Ltd.
Designer: Felix Heck , Sang-Won Yoon , Yeo-Wan Yun , Dong-Seok Lee
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公开(公告)号:USD705215S1
公开(公告)日:2014-05-20
申请号:US29440641
申请日:2012-12-24
Applicant: Samsung Electronics Co., Ltd.
Designer: Dong-Seok Lee , Ik-Sang Kim , Son-Young Lee
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公开(公告)号:US09558956B2
公开(公告)日:2017-01-31
申请号:US14789420
申请日:2015-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Bong-Cheol Kim , Eun-Shoo Han , Dong-Seok Lee
IPC: H01L21/308 , H01L21/311 , H01L21/8234 , H01L21/3213 , H01L27/108
CPC classification number: H01L21/3086 , H01L21/0337 , H01L21/32139 , H01L21/823431 , H01L27/10879 , H01L27/10897
Abstract: A method for fabricating a semiconductor device is provided, which includes forming a first mask pattern and a second mask pattern on a first layer, forming a block mask that covers the second mask pattern on the first layer, forming first spacers on side walls of the first mask pattern, exposing the second mask pattern through removal of the first mask pattern and the block mask, forming a third mask pattern and a fourth mask pattern through etching of the first layer using the first spacers and the second mask pattern as etch masks, and forming second spacers and third spacers on side walls of the third mask pattern and side walls of the fourth mask pattern, respectively.
Abstract translation: 提供了一种制造半导体器件的方法,其包括在第一层上形成第一掩模图案和第二掩模图案,形成覆盖第一层上的第二掩模图案的块掩模,在第一层的侧壁上形成第一间隔物 第一掩模图案,通过去除第一掩模图案和块掩模曝光第二掩模图案,通过使用第一间隔物和第二掩模图案作为蚀刻掩模蚀刻第一层来形成第三掩模图案和第四掩模图案, 以及分别在第三掩模图案的侧壁和第四掩模图案的侧壁上形成第二间隔物和第三间隔物。
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公开(公告)号:US09343370B1
公开(公告)日:2016-05-17
申请号:US14555775
申请日:2014-11-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Seok Lee , Kang-Ill Seo
IPC: H01L21/308 , H01L21/8234 , H01L21/762 , H01L21/311 , H01L21/3065 , H01L21/306
CPC classification number: H01L21/823431 , H01L21/3083 , H01L21/845 , H01L29/66795
Abstract: An exemplary method of fabricating a semiconductor device is provided. First and second hard mask patterns adjacent to each other are formed on a substrate. First and second active fins are formed by etching the substrate using the first and second hard mask patterns as a etch mask. An isolation layer is formed to fill a region defined by the first and second active fins and the first and second hard mask patterns. A mask pattern is formed to be positioned on the first hard mask pattern and overlap the first active fin. A first trench is formed by etching a portion of the isolation layer and a portion of the second active fin using the mask pattern as an etch mask. The remaining portion of the second active fin is removed by performing an isotropic etching process.
Abstract translation: 提供了一种制造半导体器件的示例性方法。 在基板上形成彼此相邻的第一和第二硬掩模图案。 通过使用第一和第二硬掩模图案作为蚀刻掩模蚀刻衬底来形成第一和第二活性鳍。 形成隔离层以填充由第一和第二活动鳍片以及第一和第二硬掩模图案限定的区域。 形成掩模图案以定位在第一硬掩模图案上并且与第一活动散热片重叠。 通过使用掩模图案作为蚀刻掩模蚀刻隔离层的一部分和第二有源散热片的一部分来形成第一沟槽。 通过执行各向同性蚀刻工艺来去除第二活性鳍片的剩余部分。
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