Abstract:
A clock data recovery device includes a clock recovery device for separating a recovery clock signal and a data signal from an input signal and generating a clock fail signal in response to noise of the input signal; a clock generator for receiving a control voltage to generate one or more delay clock signals, delaying the recovery clock signal to generate the delay clock signals in a first mode, delaying the generated delay clock signal to generate the delay clock signal in a second mode, and switching the first mode to the second mode in response to the clock fail signal; and a phase frequency detector for comparing at least one of the delay clock signals with the recovery clock signal to generate a voltage adjusting signal; and a control voltage generator for receiving the voltage adjusting signal to generate the control voltage.
Abstract:
A display driver circuit includes a source driver and a display driver. The source driver drives source lines of a display panel, and the timing controller transmits image data to the source driver and controls the source driver such that the transmitted image data is displayed in the display panel. The timing controller randomizes the image data in a scrambling mode when the timing controller transmits data packets including pixel data field in which the image data is written.