公开(公告)号：US20180144802A1

公开(公告)日：2018-05-24

申请号：US15607551

申请日：2017-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Min CHOI ,  Dong-Chan KIM ,  Ae-Jeong LEE ,  Moo-Rym CHOI

IPC: G11C16/22 ,  G06F12/02

CPC classification number: G11C16/225 ,  G06F12/0246 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/34

Abstract: In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.

公开(公告)号：US20170053828A1

公开(公告)日：2017-02-23

申请号：US15238836

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Hoon PARK ,  Dong-Chan KIM ,  Masayuki TOMOYASU ,  Je-Woo HAN

IPC: H01L21/768 ,  H01L21/68 ,  H01L21/8234 ,  H01L21/66

CPC classification number: H01L21/76897 ,  H01L21/682 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L22/12 ,  H01L22/20 ,  H01L29/4983

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括形成第一层间绝缘层，该第一层间绝缘层包括由第一栅极隔离物限定的第一沟槽和由衬底上的第二栅极间隔物限定的第二沟槽，形成第一栅电极，其填充第一沟槽的一部分 以及第二栅电极，其填充所述第二沟槽的一部分，形成填充所述第一栅电极上的所述第一沟槽的剩余部分的第一封盖图案，形成填充所述第二栅极上的所述第二沟槽的其余部分的第二封盖图案 形成覆盖所述第一层间绝缘层上的所述第一栅极间隔物和所述第二栅极间隔物的第二层间绝缘层，在所述第二层间绝缘层上形成第三层间绝缘层，形成贯通所述第三层间绝缘层的接触孔 以及第一栅电极和第二栅电极之间的第二层间绝缘层。