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Patent Agency Ranking
公开(公告)号：US11087839B2
公开(公告)日：2021-08-10
申请号：US16802803
申请日：2020-02-27
Inventor： Jungho Yoon , Cheol Seong Hwang , Soichiro Mizusaki , Youngjin Cho
Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.
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公开(公告)号：US12230667B2
公开(公告)日：2025-02-18
申请号：US17854679
申请日：2022-06-30
Inventor： Sang Yeol Kang , Kyu Ho Cho , Han Jin Lim , Cheol Seong Hwang
Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.
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公开(公告)号：US11574677B2
公开(公告)日：2023-02-07
申请号：US17385263
申请日：2021-07-26
Inventor： Jungho Yoon , Cheol Seong Hwang , Soichiro Mizusaki , Youngjin Cho
Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.
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公开(公告)号：US11411069B2
公开(公告)日：2022-08-09
申请号：US17030678
申请日：2020-09-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang Yeol Kang , Kyu Ho Cho , Han Jin Lim , Cheol Seong Hwang
IPC: H01L49/02 , H01L27/108
Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.
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公开(公告)号：US10825889B2
公开(公告)日：2020-11-03
申请号：US16012997
申请日：2018-06-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang Yeol Kang , Kyu Ho Cho , Han Jin Lim , Cheol Seong Hwang
IPC: H01L49/02 , H01L27/108
Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.
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