公开(公告)号：US20240147722A1

公开(公告)日：2024-05-02

申请号：US18331397

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongju Kim ,  Dongsung Choi ,  Wonjun Park ,  Donghwa Lee ,  Jaemin Jung ,  Changheon Cheon

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06551

Abstract: A semiconductor device may include a gate stack that includes a first insulating pattern, a second insulating pattern adjacent to the first insulating pattern, a third insulating pattern adjacent to the second insulating pattern, a first conductive pattern between the first and second insulating patterns, and a second conductive pattern between the second and third insulating patterns, a channel layer that extends in the gate stack, a tunnel insulating layer on the channel layer, and a first data storage pattern and a second data storage pattern on the tunnel insulating layer. The first data storage pattern may include a first outer portion between the first and second insulating patterns, and a first inner portion on the first outer portion.

公开(公告)号：US20240224523A1

公开(公告)日：2024-07-04

申请号：US18493853

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsung Choi ,  Byongju Kim ,  Wonjun Park ,  Jaemin Jung ,  Changheon Cheon

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A non-volatile memory device includes a substrate, a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers, wherein the plurality of gate electrodes are stacked in a step shape, a channel structure that extends through the mold structure, and a cell contact that extends through the mold structure, the cell contact is connected to a first gate electrode, and the cell contact is not electrically connected to a second gate electrode among the plurality of gate electrodes, wherein the first gate electrode includes: an extension portion; a pad portion having a vertical thickness greater than a vertical thickness of the extension portion; and a connection portion that electrically connects the pad portion to the cell contact, the connection portion has a vertical thickness less than a vertical thickness of the pad portion, and one or more first insulating rings on the connection portion.

公开(公告)号：US20240206180A1

公开(公告)日：2024-06-20

申请号：US18341066

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsung Choi ,  Byongju Kim ,  Youjung Kim ,  Chaeho Kim ,  Changheon Cheon

IPC: H01L29/792

CPC classification number: H10B43/35 ,  H10B43/27

Abstract: A vertical non-volatile memory device may include a mold structure including first and second insulation patterns and a first gate electrode, a semiconductor pattern extending through the mold structure in a first direction, a first charge insulation layer between the first insulation pattern and the semiconductor pattern, a second charge insulation layer spaced apart from the first charge insulation layer and between the second insulation pattern and the semiconductor pattern, a charge storage layer between the first and second charge insulation layers and between the first gate electrode and the semiconductor pattern, and a first blocking insulation layer between the first gate electrode and the charge storage layer, and a first length in the first direction of the first gate electrode is shorter than a second length in the first direction of a first surface of the charge storage layer which is in contact with the first blocking insulation layer.

公开(公告)号：US20240074195A1

公开(公告)日：2024-02-29

申请号：US18308262

申请日：2023-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongju Kim ,  Dongsung Choi ,  Wonjun Park ,  Donghwa Lee ,  Jaemin Jung ,  Changheon Cheon

IPC: H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a conductive pattern, an insulating pattern, a channel film extending in a vertical direction inside a channel hole, a charge trap pattern between the conductive pattern and the channel film inside the channel hole, a tunneling dielectric film between the charge trap pattern and the channel film, and a blocking dielectric film extending between the conductive pattern and the charge trap pattern and between the insulating pattern and the tunneling dielectric film. The insulating pattern includes a first insulating pattern overlapping the conductive pattern in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film. The first insulating pattern has a first dielectric constant, and the second insulating pattern has a second dielectric constant that is lower than the first dielectric constant.