公开(公告)号：US20190013260A1

公开(公告)日：2019-01-10

申请号：US16131182

申请日：2018-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kun-sang PARK ,  Son-kwan HWANG ,  Ji-soon PARK ,  Byung-lyul PARK

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

公开(公告)号：US20170345713A1

公开(公告)日：2017-11-30

申请号：US15638551

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-lyul PARK ,  Hyun-soo CHUNG ,  Gil-heyun CHOI ,  Son-kwan HWANG

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

公开(公告)号：US20170207158A1

公开(公告)日：2017-07-20

申请号：US15408977

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-kyu KANG ,  Ho-jin LEE ,  Byung-lyul PARK ,  Tae-yeong KIM ,  Seok-ho KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2225/06548

Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.