公开(公告)号：US20140162427A1

公开(公告)日：2014-06-12

申请号：US14082280

申请日：2013-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Yong GWAK

IPC: H01L21/306 ,  H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A method of forming a fine pattern includes forming first line mask patterns on a mask layer to extend along a direction, forming second line mask patterns to extend along a diagonal direction with respect to the first line mask patterns, anisotropically etching the mask layer exposed by the first and second line mask patterns to form elliptical openings, and isotropically etching the mask layer provided with the openings to form a mask pattern with enlarged openings.

Abstract translation: 形成精细图案的方法包括在掩模层上形成第一线掩模图案以沿着方向延伸，形成第二线掩模图案以相对于第一线掩模图案沿对角线方向延伸，各向异性地蚀刻由 第一和第二线掩模图案以形成椭圆形开口，并且各向同性地蚀刻设置有开口的掩模层，以形成具有扩大开口的掩模图案。

公开(公告)号：US20150171163A1

公开(公告)日：2015-06-18

申请号：US14481932

申请日：2014-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mong-Sup LEE ,  Byoung-Yong GWAK ,  Byung-Ho KWAK ,  Yoon-Kyung KIM ,  Tae-Joon PARK ,  Byung-Sul RYU ,  In-Seak HWANG

IPC: H01L29/06

CPC classification number: H01L21/762 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括沿第一方向延伸的第一位线结构，在第一方向上延伸并与第一位线结构间隔开的第二位线结构，位于第一位线结构和第二位之间的存储接触插塞 线结构，并且在垂直于第一方向的第二方向上延伸;第一插塞绝缘体，位于第一位线结构和第二位线结构之间，并且被配置为接触沿着存储接触插塞的第二方向延伸的侧表面 以及位于第一位线结构和第一插塞绝缘体之间的插头隔离图案。

公开(公告)号：US20150093895A1

公开(公告)日：2015-04-02

申请号：US14503662

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Yong GWAK

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/108 ,  H01L21/283

CPC classification number: H01L21/32134 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91 ,  H01L28/92

Abstract: Fabricating methods of a semiconductor device are provided. The fabricating methods may include forming a mold layer, forming a catalyst pattern including noble metal on the mold layer and etching the mold layer using the catalyst pattern as a catalyst. Etching the mold layer may include performing a wet etching process.

Abstract translation: 提供半导体器件的制造方法。 制造方法可以包括形成模具层，在模具层上形成包括贵金属的催化剂图案，并使用催化剂图案作为催化剂蚀刻模具层。 蚀刻模具层可以包括执行湿蚀刻工艺。

公开(公告)号：US20130230961A1

公开(公告)日：2013-09-05

申请号：US13688840

申请日：2012-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyong-Soo KIM ,  Byoung-Yong GWAK ,  Kukhan YOON

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10805 ,  H01L27/10852 ,  H01L28/91

Abstract: According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.

Abstract translation: 根据本发明构思的示例性实施例，形成半导体存储器件的方法包括在衬底上顺序地形成第一模具层，第一支撑层，第二模具层和第二支撑层，形成穿透第二支撑层的下部电极 第二模具层，第一支撑层和第一模具层，图案化第二支撑层以形成包括开口的第二支撑图案，去除第二模具层以暴露下部电极的侧壁部分， 并蚀刻下电极的暴露的侧壁。