BANKING REGISTER RENAMING TO REDUCE POWER
    1.
    发明申请

    公开(公告)号:US20180329711A1

    公开(公告)日:2018-11-15

    申请号:US15657076

    申请日:2017-07-21

    Inventor: Ankit GHIYA

    Abstract: According to one general aspect, an apparatus may include a register circuit and an instruction scheduler circuit. The register circuit may include a plurality of physical registers that are partitioned into at least a common portion that is associated with a predefined plurality of instructions, and a shared portion, and a plurality of write ports, wherein each portion is associated with at least one respective write port. The instruction scheduler circuit configured to determine an instruction, and rename an architectural register associated with the instruction to a physical register. Wherein the portion including the physical register is selected based, at least in part, upon a characteristic of the current instruction.

    INTEGRATED CONFIRMATION QUEUES
    2.
    发明申请

    公开(公告)号:US20180329821A1

    公开(公告)日:2018-11-15

    申请号:US15665401

    申请日:2017-07-31

    Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a series of memory addresses to be pre-fetched from the memory system. The confirmation queue circuit may be configured to: maintain a windowed confirmation queue of predicted memory addresses, compare a requested memory address against the predicted memory addresses, and, if the requested memory address is included in the predicted memory addresses, indicate that a successful pre-fetch has occurred.

Patent Agency Ranking