Thin film transistor array panel and manufacturing method of the same
    1.
    发明授权
    Thin film transistor array panel and manufacturing method of the same 有权
    薄膜晶体管阵列及其制造方法相同

    公开(公告)号:US09570477B2

    公开(公告)日:2017-02-14

    申请号:US15041746

    申请日:2016-02-11

    Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.

    Abstract translation: 薄膜晶体管(“TFT”)阵列面板包括: 绝缘基板,设置在所述绝缘基板上并包括漏电极的TFT,覆盖所述TFT的钝化层,并且包括设置在其中的所述漏电极对应的接触部分,所述隔板包括设置在所述钝化层上的有机材料,并且包括 横向部分,纵向部分和设置在漏电极上的接触部分,设置在钝化层上并设置在由隔板限定的区域中的滤色器,设置在隔板上的有机覆盖层和滤色器,以及 设置在所述有机覆盖层上的像素电极,并且通过所述钝化层的接触部分和所述隔离物的接触部分连接到所述漏电极,其中在所述有机覆盖层中形成接触孔,所述接触孔对应于所述钝化层的接触部分 钝化层。

    Display device and driving method thereof

    公开(公告)号:US10223958B2

    公开(公告)日:2019-03-05

    申请号:US14880890

    申请日:2015-10-12

    Abstract: A display device includes a first unit pixel disposed in a first pixel column and a first pixel row, and a second unit pixel disposed in the first pixel column and a second pixel row adjacent to the first pixel row, and first and second gate lines extending in a row direction and having gate voltage input pads at a terminal portion thereof. First and second data lines extend in a column direction and are connected to the first unit pixel and the second unit pixel, respectively. A first charge control line extends in the row direction and has a charge control gate voltage input pad disposed at a terminal portion thereof. The first gate line is connected to the first unit pixel and the second gate line is connected to the second unit pixel. The first gate line and the second gate line simultaneously receive a same gate pulse.

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