Abstract:
In a thin film transistor, first and second thin film transistors are connected to an Nth gate line and an Mth data line, and first and second sub pixel electrodes are connected to the first and second thin film transistors, respectively. A third thin film transistor includes a gate electrode connected to an (N+1)th gate line, a semiconductor layer overlapping with the gate electrode, a source electrode connected to the second sub pixel electrode and partially overlapping with the gate electrode, and a drain electrode facing the source electrode. A first auxiliary electrode is connected to the drain electrode and arranged on the same layer as the first and second sub pixel electrodes. An opposite electrode is arranged on the same layer as the gate line and at least partially overlaps with the first auxiliary electrode with at least one insulating layer disposed therebetween.
Abstract:
A liquid crystal display, including: a first substrate and a second substrate; a liquid crystal layer; a first data line disposed on the first substrate; a pixel electrode disposed on the first substrate; and a common electrode disposed on the first substrate and overlapping at least a portion of the pixel electrode and the first data line. One of the pixel electrode and the common electrode includes a plurality of branch electrodes spaced apart from each other and the other of has an at least approximately planar shape that is substantially parallel to a surface of at least one of the first substrate and the second substrate. The display can also include a passivation layer having a dielectric constant of about 3.5 or less, and including a first portion disposed between the common electrode and the first data line.
Abstract:
A method for manufacturing a liquid crystal display (“LCD”) includes; disposing a gate line including a gate electrode on a substrate, disposing a gate insulating layer on the gate line, disposing a data layer including a data line, source electrode and a drain electrode facing the source electrode on the gate insulating layer, disposing a color filter on the gate insulating layer, disposing an overcoat layer on the color filter, disposing a planarization layer on a portion of the overcoat layer corresponding to the gate line, the data line and the drain electrode, and disposing a pixel electrode in contacted with the overcoat layer in a region corresponding to the color filter.