Abstract:
An LCD device includes first and second substrates and a liquid crystal layer disposed between the substrates. A gate transmitting member is disposed on the first substrate. The gate transmitting member includes a gate line and a gate electrode. A data transmitting member is disposed on the first substrate. The data transmitting member includes a data line, a source electrode, and a drain electrode. A pixel electrode is disposed in a pixel area. The pixel electrode is connected to the source electrode. A first gate insulating layer is disposed on the gate transmitting member. The first gate insulating layer has substantially a same shape as the gate transmitting member and has a greater size than a size of the gate transmitting member. A semiconductor layer is disposed on the first gate insulating layer. The semiconductor layer overlaps the gate electrode, the source electrode, and the drain electrode.
Abstract:
An LCD device includes first and second substrates and a liquid crystal layer disposed between the substrates. A gate transmitting member is disposed on the first substrate. The gate transmitting member includes a gate line and a gate electrode. A data transmitting member is disposed on the first substrate. The data transmitting member includes a data line, a source electrode, and a drain electrode. A pixel electrode is disposed in a pixel area. The pixel electrode is connected to the source electrode. A first gate insulating layer is disposed on the gate transmitting member. The first gate insulating layer has substantially a same shape as the gate transmitting member and has a greater size than a size of the gate transmitting member. A semiconductor layer is disposed on the first gate insulating layer. The semiconductor layer overlaps the gate electrode, the source electrode, and the drain electrode.
Abstract:
A gate driving circuit includes a pull-up control part applying a previous carry signal of one of previous stages to a first node in response to the previous carry signal, a pull-up part outputting a clock signal as an N-th gate output signal in response to a signal at the first node, a carry part outputting the clock signal as an N-th carry signal in response to the signal at the first node, a first pull-down part pulling down the signal at the first node to a second off voltage in response to a first next carry signal of one of next stages and a second pull-down part pulling down the N-th gate output signal to a first off voltage in response to a second next carry signal of one of the next stages different from the first next carry signal.