公开(公告)号：US08848152B2

公开(公告)日：2014-09-30

申请号：US13924081

申请日：2013-06-21

Applicant: Samsung Display Co., Ltd.

Inventor： Seon-Kyoon Mok ,  Si-Hyun Ahn ,  Woo-Jung Shin ,  Byoung-Sun Na ,  So-Young Kim

IPC: G02F1/1345 ,  G09G3/36 ,  G02F1/1362 ,  G02F1/133

CPC classification number: G02F1/136286 ,  G02F1/133 ,  G02F1/1345 ,  G09G3/3696

Abstract: A display substrate includes a plurality of gate lines extending in a first direction and arranged in a second direction in a display area of the display substrate, an alignment film formed in the display area and in an end area adjacent to end portions of the gate lines in a peripheral area surrounding the display area, and a plurality of circuit stages formed in the end area to connect to the gate lines and a dummy stage connected to a last circuit stage of the circuit stages. Each of the circuit stages includes a gate driving circuit disposed at the higher portion the gate line corresponding to the circuit stages and a gate connecting line formed in the peripheral area between the display area and the gate driving circuit to connect each of the circuit stages with each of the gate lines.

Abstract translation: 显示基板包括在显示基板的显示区域中沿第一方向延伸并沿第二方向布置的多条栅极线，形成在显示区域中的取向膜和与栅极线的端部相邻的端部区域 在围绕显示区域的外围区域中，以及形成在端部区域中以连接到栅极线的多个电路级以及连接到电路级的最后电路级的虚拟级。 每个电路级包括设置在对应于电路级的栅极线的较高部分处的栅极驱动电路和形成在显示区域和栅极驱动电路之间的周边区域中的栅极连接线，以将每个电路级与每个电路级连接 每条门线。

公开(公告)号：US09490274B2

公开(公告)日：2016-11-08

申请号：US14700283

申请日：2015-04-30

Applicant: Samsung Display Co., Ltd.

Inventor： Hyung Jun Park ,  Kyung-Ho Park ,  Woo-Jung Shin ,  Si Hyun Ahn ,  Dong-Hyun Yoo

IPC: H01L27/12 ,  H01L29/417

CPC classification number: H01L27/124 ,  G02F1/136213 ,  G02F1/13624 ,  G02F2001/134345 ,  G02F2001/136245 ,  H01L29/41733 ,  H01L29/41758

Abstract: A thin film transistor array panel includes a first substrate; a gate line and a data line on the first substrate; a storage electrode line on the first substrate where a constant voltage is applied thereto; a first thin film transistor and a second thin film transistor which are connected to the gate line and the data line; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor.