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公开(公告)号：US20220029021A1
公开(公告)日：2022-01-27
申请号：US17349214
申请日：2021-06-16
Inventor： TAESANG KIM , MIN SEONG KIM , HYUN JAE KIM , JUN HYUNG LIM
IPC: H01L29/786 , H01L29/24 , H01L29/10 , H01L27/12
Abstract: A transistor includes a gate electrode, an active layer facing the gate electrode, and a source electrode and a drain electrode connected to the active layer. The active layer includes a lower active layer including an oxide-based semiconductor material, and an upper active layer including the oxide-based semiconductor material and an oxygen-gettering material.
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Patent Agency Ranking
2.发明公开公开(公告)号：US20240065073A1
公开(公告)日：2024-02-22
申请号：US18201982
申请日：2023-05-25
Inventor： TAESANG KIM , Hyun Jae KIM , Hyukjoon YOO , JUN HYUNG LIM
IPC: H10K59/65 , H01L31/0224 , H01L31/032 , H01L31/113 , H01L31/18
CPC classification number: H10K59/65 , H01L31/022466 , H01L31/032 , H01L31/1136 , H01L31/18 , G06V40/1318
Abstract: A phototransistor includes a gate electrode, a semiconductor layer disposed on the gate electrode, a gate insulating layer disposed between the gate electrode and the semiconductor layer, a source electrode, a drain electrode, and a porous layer disposed on the source electrode, the semiconductor layer, and the drain electrode, where a plurality of holes is defined in the porous layer.
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公开(公告)号：US20240282248A1
公开(公告)日：2024-08-22
申请号：US18530609
申请日：2023-12-06
Applicant: Samsung Display Co., Ltd.
Inventor： EOK SU KIM , JONGDO KEUM , TAESANG KIM
IPC: G09G3/32 , G09G3/3266
CPC classification number: G09G3/32 , G09G3/3266 , G09G2310/0267
Abstract: A scan driving circuit includes multiple stages. A j-th stage of the stages includes a buffer part electrically connected to an output terminal that operates in response to a potential of a first control node, a holding part electrically connected to the output terminal that operates in response to a potential of a second control node, and an inverter part electrically connected to the first and second control nodes that controls the potentials of the first and second nodes. The inverter part includes a control transistor including a gate electrically connected to the first control node, and a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage. The control transistor includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.
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公开(公告)号：US20220181465A1
公开(公告)日：2022-06-09
申请号：US17652843
申请日：2022-02-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： JAYBUM KIM , SERYEONG KIM , JUNHYUNG LIM , TAESANG KIM
IPC: H01L29/66 , H01L27/32 , H01L29/786 , H01L27/146 , H01L29/04 , H01L27/12
Abstract: A semiconductor device includes a base substrate. A first thin-film transistor is disposed on the base substrate. The first thin-film transistor includes a first input electrode, a first output electrode, a first semiconductor pattern disposed below a first insulating layer, and a first control electrode disposed on the first insulating layer and below a second insulating layer. A second thin-film transistor includes a second input electrode, a second output electrode, a second semiconductor pattern disposed on the second insulating layer, and a second control electrode disposed on an insulating pattern formed on the second semiconductor pattern and exposes a portion of the second semiconductor pattern. The first semiconductor pattern includes a crystalline semiconductor. The second semiconductor pattern incudes an oxide semiconductor. The first semiconductor pattern, the first control electrode, the second semiconductor pattern, and the second control electrode are overlapped.
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公开(公告)号：US20240257724A1
公开(公告)日：2024-08-01
申请号：US18513917
申请日：2023-11-20
Applicant: Samsung Display Co., LTD.
Inventor： EOK SU KIM , JONGDO KEUM , TAESANG KIM
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0267 , G09G2310/0294 , G09G2310/061 , G09G2310/08
Abstract: A gate driving circuit includes: a first pull-up control circuit, a pull-up circuit, a pull-down circuit and an inverting circuit. The first pull-up control circuit applies a previous carry signal which is one of carry signals of previous stages to a first control node in response to the previous carry signal. The pull-up circuit outputs a gate clock signal as a gate output signal in response to a signal of the first control node. The pull-down circuit outputs a second low voltage as the gate output signal in response to a first next carry signal which is one of carry signals of next stages. The inverting circuit outputs one of a first signal and a first low voltage to a third control node in response to the first signal and a signal of a second control node.
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公开(公告)号：US20200219991A1
公开(公告)日：2020-07-09
申请号：US16824339
申请日：2020-03-19
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： JAYBUM KIM , SERYEONG KIM , JUNHYUNG LIM , TAESANG KIM
IPC: H01L29/66 , H01L27/12 , H01L27/32 , H01L29/04 , H01L27/146 , H01L29/786
Abstract: A semiconductor device includes a base substrate. A first thin-film transistor is disposed on the base substrate. The first thin-film transistor includes a first input electrode, a first output electrode, a first semiconductor pattern disposed below a first insulating layer, and a first control electrode disposed on the first insulating layer and below a second insulating layer. A second thin-film transistor includes a second input electrode, a second output electrode, a second semiconductor pattern disposed on the second insulating layer, and a second control electrode disposed on an insulating pattern formed on the second semiconductor pattern and exposes a portion of the second semiconductor pattern. The first semiconductor pattern includes a crystalline semiconductor. The second semiconductor pattern includes an oxide semiconductor. The first semiconductor pattern, the first control electrode, the second semiconductor pattern, and the second control electrode are overlapped.
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