公开(公告)号：US20170154590A1

公开(公告)日：2017-06-01

申请号：US15229798

申请日：2016-08-05

Applicant: Samsung Display Co., Ltd.

Inventor： Sihyun Ahn ,  Yanghee Kim ,  Jaewon Kim ,  Seungsoo Baek

IPC: G09G3/36

CPC classification number: G09G3/3655 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/043 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/02

Abstract: A gate driving circuit includes a plurality of driving stages configured to output a plurality of gates signals, a k-th driving stage (where k is a natural number greater than 2) being configured to receive a clock signal, a (k−1)-th carry signal from a (k−1)-th driving stage, a (k+1)-th carry signal from a (k+1)-th driving stage, a (k+2)-th carry signal from a (k+2)-th driving stage, a first ground voltage, a second ground voltage, and a third ground voltage, and to output a k-th gate signal and a k-th carry signal, and wherein the k-th driving stage comprises a first pull-down circuit configured to discharge the k-th gate signal to the third ground voltage in response to the (k+1)-th carry signal, wherein the third ground voltage changes within a range during a single frame section in which the plurality of driving stages sequentially outputs the plurality of gate signals.

公开(公告)号：US10127876B2

公开(公告)日：2018-11-13

申请号：US15159721

申请日：2016-05-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kye-uk Lee ,  Kee-bum Park ,  Sihyun Ahn ,  Jaewon Kim ,  Byoungsun Na ,  Yoomi Ra

IPC: G09G3/36 ,  G09G3/20

Abstract: A gate driving circuit includes a plurality of stages, a k-th stage (where k is a natural number) of the plurality of stages being configured to receive a clock signal, a (k−1)-th carry signal from a (k−1)-th stage of the plurality of stages, a (k+1)-th carry signal from a (k+1)-th stage of the plurality of stages, a (k+2)-th carry signal from a (k+2)-th stage of the plurality of stages, a first ground voltage, a second ground voltage, and a third ground voltage, and to output a k-th gate signal and a k-th carry signal, the k-th stage including a first pull down circuit configured to discharge the k-th gate signal as the third ground voltage in response to the (k+1)-th carry signal, and the third ground voltage having a lower voltage level than the first ground voltage and having a higher voltage level than the second ground voltage.

公开(公告)号：US20170084239A1

公开(公告)日：2017-03-23

申请号：US15159721

申请日：2016-05-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kye-uk Lee ,  Kee-bum Park ,  Sihyun Ahn ,  Jaewon Kim ,  Byoungsun Na ,  Yoomi Ra

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3677 ,  G09G3/2003 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2230/00 ,  G09G2310/0286 ,  G09G2320/02 ,  G11C19/28

Abstract: A gate driving circuit includes a plurality of stages, a k-th stage (where k is a natural number) of the plurality of stages being configured to receive a clock signal, a (k−1)-th carry signal from a (k−1)-th stage of the plurality of stages, a (k+1)-th carry signal from a (k+1)-th stage of the plurality of stages, a (k+2)-th carry signal from a (k+2)-th stage of the plurality of stages, a first ground voltage, a second ground voltage, and a third ground voltage, and to output a k-th gate signal and a k-th carry signal, the k-th stage including a first pull down circuit configured to discharge the k-th gate signal as the third ground voltage in response to the (k+1)-th carry signal, and the third ground voltage having a lower voltage level than the first ground voltage and having a higher voltage level than the second ground voltage.