CLOCK GENERATOR AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20210225291A1

    公开(公告)日:2021-07-22

    申请号:US17021430

    申请日:2020-09-15

    Abstract: A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

    CLOCK GENERATOR AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20240395217A1

    公开(公告)日:2024-11-28

    申请号:US18791092

    申请日:2024-07-31

    Abstract: A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

    DISPLAY DEVICE
    4.
    发明申请

    公开(公告)号:US20250014513A1

    公开(公告)日:2025-01-09

    申请号:US18895394

    申请日:2024-09-25

    Abstract: The current disclosure relates to a display device including a display panel including a plurality of pixels, and a plurality of gate lines and a plurality of data lines connected to the plurality of pixels, a gate driver applying a gate signal to the plurality of gate lines, a data driver applying a data signal to the plurality of data lines, and a voltage provider configured to generate a gate-on voltage that is gradually changed in one frame and a kickback voltage that is gradually changed in one frame to transmit the gate-on voltage and the kickback voltage to the gate driver.

    CLOCK GENERATOR AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20230162688A1

    公开(公告)日:2023-05-25

    申请号:US18158349

    申请日:2023-01-23

    CPC classification number: G09G3/3266 G09G3/3275 G09G3/3233

    Abstract: A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

    POWER MANAGEMENT DRIVER AND DISPLAY DEVICE HAVING THE SAME

    公开(公告)号:US20220293058A1

    公开(公告)日:2022-09-15

    申请号:US17832179

    申请日:2022-06-03

    Abstract: A power management driver and a display device having the power management driver are provided, including a first power supply configured to supply a first voltage to a first driving power terminal of a pixel through a power line during a sensing period, and supply a second voltage to the first driving power terminal of the pixel through the power line during a display period; a controller configured to control timing at which the first voltage is output and timing at which the second voltage is output during a transition period between the display period and the sensing period in response to a sensing control signal; and a fault detector configured to detect a fault in the power line based on a current flowing through an output terminal during the sensing period.

    DISPLAY DEVICE AND METHOD OF DRIVING THE SAME

    公开(公告)号:US20210209989A1

    公开(公告)日:2021-07-08

    申请号:US17081427

    申请日:2020-10-27

    Abstract: A display device includes a display panel including a plurality of pixels, a scan driver which supplies scan signals and sensing control signals to scan lines and sensing control lines, based on a clock signal, a power manager which applies initialization power to initialization lines, a sensor which senses threshold voltages of driving transistors, a detector which detects an error of the initialization lines and outputs line information indicating an initialization line having the error, a timing controller which changes a sensed threshold voltage using the initialization line having the error and generates image data with reference to a changed threshold voltage, and a data driver which supplies a data signal corresponding to the image data to data lines.

    DISPLAY DEVICE
    8.
    发明申请

    公开(公告)号:US20210142714A1

    公开(公告)日:2021-05-13

    申请号:US16917740

    申请日:2020-06-30

    Abstract: A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

    DISPLAY DEVICE AND METHOD OF DRIVING THE SAME

    公开(公告)号:US20240046868A1

    公开(公告)日:2024-02-08

    申请号:US18137485

    申请日:2023-04-21

    Abstract: The present inventive concept provides a display device including a pixel unit which includes pixels, a sensing unit connected to the pixels through sensing lines, a first power voltage generator connected to the pixels through a first power line and generating a first power voltage for driving the pixels, a second power voltage generator connected to the pixels through the first power line and generating a second power voltage for sensing the pixels, and a timing controller selectively controlling operations of the first power voltage generator and the second power voltage generator according to a driving method of the pixel unit, and a method driving the same.

    DISPLAY DEVICE AND DRIVING METHOD THEREOF

    公开(公告)号:US20220076624A1

    公开(公告)日:2022-03-10

    申请号:US17236481

    申请日:2021-04-21

    Abstract: A display device includes a first power source, a timing controller, and pixels. The timing controller is connected to the first power source through a main line, an auxiliary line, and a detection line. The pixels are commonly connected to the first power source through a first power line. The first power source includes: a main power source connected to the first power line and the main line; an auxiliary power source connected to the auxiliary line; a rectifier connected between the auxiliary power source and the first power line; and a comparator comparing a voltage of the first power line and providing its output to the detection line.

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