公开(公告)号：US20170206821A1

公开(公告)日：2017-07-20

申请号：US15388933

申请日：2016-12-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： MIN-TAK LEE ,  KYU-SEOK KIM ,  SOO-YOUNG KIM ,  YOUNG-NAM YUN ,  HYUN-KOO LEE

IPC: G09G3/20 ,  G09G3/36 ,  G09G3/3275 ,  G09G3/3225 ,  G09G3/3266

CPC classification number: G09G3/2011 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3611 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0646 ,  G09G2340/0492 ,  G09G2360/145 ,  G09G2360/16 ,  H01L21/02678 ,  H01L21/02686 ,  H01L27/1274

Abstract: A method of compensating for Mura in a display panel includes displaying a high gray-scale image and a low gray-scale image on a display panel. The displayed images are photographed to generate a high gray-scale luminance image and a low gray-scale luminance image. An ELA Mura for-measurement image having moiré-removed luminance values is generated by dividing luminance values of the low gray-scale luminance image by luminance values of the high gray-scale luminance image. One-dimensional average data is obtained from the ELA Mura for-measurement image. The one-dimensional average data is transformed into frequency-domain data. Target frequency-domain data having a maximum peak value is identified from the frequency-domain data. A direction, an intensity, and a frequency of the ELA Mura are obtained from the target frequency-domain data. A filter is determined based on the obtained information. The filter is applied to image data.

公开(公告)号：US20220223112A1

公开(公告)日：2022-07-14

申请号：US17524655

申请日：2021-11-11

Applicant: Samsung Display Co., Ltd.

Inventor： SUNGYUP KIM ,  SUNYOUNG PARK ,  TAE-HO KIM ,  JONGUK BANG ,  MIN-TAK LEE ,  JOON HUH

IPC: G09G3/3283

Abstract: A pixel and a display device including the pixel are disclosed. The pixel comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a light emitting element. The eighth transistor includes a gate electrode configured to receive a second data voltage, a first electrode connected to a fourth node, and a second electrode configured to receive an initialization voltage. The eighth transistor adjusts a voltage level of the first capacitor based on a difference between the voltage level of the first capacitor and a level of the second data voltage.