公开(公告)号：US09406807B2

公开(公告)日：2016-08-02

申请号：US14290788

申请日：2014-05-29

Applicant: Samsung Display Co., Ltd.

Inventor： Joo-Han Kim ,  Hwa-Dong Jung ,  Wan-Soon Lim ,  Jee-Hun Lim ,  Joo Seok Yeom ,  Tae-Kyung Yim ,  Jae-Hak Lee ,  Hyuk Soon Kwon ,  Hyoung Cheol Lee ,  Jeong-Ju Park ,  Se-Myung Kwon ,  So-Young Koo

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78663 ,  H01L27/1222 ,  H01L27/1285

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract translation: 本发明的示例性实施例公开了一种制造薄膜晶体管阵列面板的方法，其具有缩短的总体处理时间并提供均匀的结晶。 本发明的示例性实施例还公开了一种薄膜晶体管的结晶方法，包括在基板上形成包括第一像素区域，第二像素区域和第三像素区域的半导体层。 结晶方法包括使用微透镜阵列结晶对应于薄膜晶体管的沟道区的半导体层的一部分。

公开(公告)号：US09171864B2

公开(公告)日：2015-10-27

申请号：US14249199

申请日：2014-04-09

Applicant: Samsung Display Co., LTD.

Inventor： Xinxing Li ,  Do-Hyun Kim ,  Chan-Woo Yang ,  Jeong-Ju Park ,  Jun-Hyun Park ,  Xun Zhu

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1259 ,  H01L27/1288

Abstract: A display substrate includes a gate metal pattern including a gate line disposed on a base substrate and a gate electrode electrically connected with the gate line, an active pattern entirely overlapped with the gate metal pattern and comprising an oxide semiconductor and a data metal pattern disposed on the active pattern and including a data line, a source electrode electrically connected with the gate line and a drain electrode spaced apart from the source electrode. The active pattern has an overlapped region in which the active pattern is overlapped with the source electrode and the drain electrode and an exposed region in which the active pattern is not overlapped with the source electrode and the drain electrode. The thickness of the overlapping region and a thickness of the exposing region are same.

Abstract translation: 显示基板包括栅极金属图案，其包括设置在基底基板上的栅极线和与栅极线电连接的栅电极，与栅极金属图案完全重叠的有源图案，并且包括氧化物半导体和数据金属图案， 所述有源图案包括数据线，与所述栅极线电连接的源电极和与所述源电极间隔开的漏电极。 有源图案具有重叠区域，其中有源图案与源电极和漏电极重叠，并且有源图案不与源电极和漏电极重叠的曝光区域。 重叠区域的厚度和曝光区域的厚度相同。

公开(公告)号：US20140264350A1

公开(公告)日：2014-09-18

申请号：US14290788

申请日：2014-05-29

Applicant: Samsung Display Co., Ltd.

Inventor： Joo-Han KIM ,  Hwa-Dong Jung ,  Wan-Soon Lim ,  Jee-Hun Lim ,  Joo Seok Yeom ,  Tae-Kyung Yim ,  Jae-Hak Lee ,  Hyuk Soon Kwon ,  Hyoung Cheol Lee ,  Jeong-Ju Park ,  Se-Myung Kwon ,  So-Young Koo

IPC: H01L29/786

CPC classification number: H01L29/78663 ,  H01L27/1222 ,  H01L27/1285

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract translation: 本发明的示例性实施例公开了一种制造薄膜晶体管阵列面板的方法，其具有缩短的总体处理时间并提供均匀的结晶。 本发明的示例性实施例还公开了一种薄膜晶体管的结晶方法，包括在基板上形成包括第一像素区域，第二像素区域和第三像素区域的半导体层。 结晶方法包括使用微透镜阵列结晶对应于薄膜晶体管的沟道区的半导体层的一部分。