公开(公告)号：US20180315369A1

公开(公告)日：2018-11-01

申请号：US15945263

申请日：2018-04-04

Applicant: Samsung Display Co., Ltd.

Inventor： KIHYUN PYUN ,  HYEON-DO PARK

IPC: G09G3/20

Abstract: A display apparatus includes a display panel including a plurality of first gate lines, a first gate driver connected to first ends of the plurality of first gate lines, a second gate driver connected to second ends of the plurality of first gate lines, a feedback line connected adjacent to the first end of one of the plurality of first gate lines, and a gate delay sensing circuit connected to the feedback line. The gate delay sensing circuit includes a time-to-digital converter and a digital comparator. The time-to-digital converter converts an activation time of a feedback gate signal into a digital activation value. The feedback gate signal is retrieved from the feedback line. The digital comparator generates a digital delay value based on the digital activation value. The digital delay value indicates resistive-capacitive (“RC”) delay of the one of the plurality of first gate lines connected to the feedback line.

公开(公告)号：US20250072215A1

公开(公告)日：2025-02-27

申请号：US18641742

申请日：2024-04-22

Applicant: Samsung Display Co., Ltd.

Inventor： YOUNGGU KANG ,  HYEON-DO PARK ,  HYUN-SUNG PARK ,  YU DEOK SEO

IPC: H10K59/121 ,  H10K59/131

Abstract: A test panel includes: a pixel; a first test element connected to the pixel, the first test element including a gate electrode, a semiconductor layer, a first electrode, and a second electrode connected to the pixel; a test pad spaced apart from the first test element; a first connecting line connected to the first test element and the test pad; and a first resistive layer in a same layer as the semiconductor layer and connecting the first electrode and the first connecting line spaced apart from each other.

公开(公告)号：US20200234630A1

公开(公告)日：2020-07-23

申请号：US16840837

申请日：2020-04-06

Applicant: Samsung Display Co., Ltd.

Inventor： KIHYUN PYUN ,  HYEON-DO PARK

IPC: G09G3/20 ,  G09G3/36

Abstract: A display apparatus includes a display panel including a plurality of first gate lines, a first gate driver connected to first ends of the plurality of first gate lines, a second gate driver connected to second ends of the plurality of first gate lines, a feedback line connected adjacent to the first end of one of the plurality of first gate lines, and a gate delay sensing circuit connected to the feedback line. The gate delay sensing circuit includes a time-to-digital converter and a digital comparator. The time-to-digital converter converts an activation time of a feedback gate signal into a digital activation value. The feedback gate signal is retrieved from the feedback line. The digital comparator generates a digital delay value based on the digital activation value. The digital delay value indicates resistive-capacitive (“RC”) delay of the one of the plurality of first gate lines connected to the feedback line.