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公开(公告)号:US20190157367A1
公开(公告)日:2019-05-23
申请号:US16250642
申请日:2019-01-17
Applicant: Samsung Display Co., Ltd.
Inventor: DONG HEE LEE , Hyun Ju Kang , Sang Won Shin
IPC: H01L27/32 , H01L29/423 , H01L27/12 , H01L29/49 , H01L29/786
CPC classification number: H01L27/3262 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L29/42384 , H01L29/4908 , H01L29/518 , H01L29/78606 , H01L29/78618 , H01L29/78645 , H01L29/7869 , H01L29/78696 , H01L2227/323
Abstract: An exemplary embodiment of the present invention provides a thin film transistor array panel and an organic light emitting diode display including the same including a substrate, a semiconductor disposed on the substrate, a first gate insulation layer disposed on the semiconductor, and a first diffusion barrier layer disposed on the first gate insulation layer. A second diffusion barrier layer is disposed on a lateral surface of the first diffusion barrier layer. A first gate electrode is disposed on the first diffusion barrier layer. A source electrode and a drain electrode are connected to the semiconductor. The first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.
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公开(公告)号:US20170358688A1
公开(公告)日:2017-12-14
申请号:US15436011
申请日:2017-02-17
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: DONG HEE LEE , GWANG MIN CHA , DONG MIN LEE
IPC: H01L29/786 , H01L27/12 , G02F1/1362 , G02F1/1368 , H01L27/32
CPC classification number: H01L29/78633 , G02F1/136209 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/13685 , H01L27/1218 , H01L27/124 , H01L27/1244 , H01L27/3248 , H01L27/3262 , H01L27/3272 , H01L27/3276 , H01L29/4908 , H01L29/78603 , H01L29/78618 , H01L29/78648 , H01L29/7869
Abstract: A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate.
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