公开(公告)号：US20160062162A1

公开(公告)日：2016-03-03

申请号：US14664189

申请日：2015-03-20

Applicant: Samsung Display Co., LTD.

Inventor： Hyun-Ju KANG ,  Sang-Woo SOHN ,  Sang-Won SHIN ,  Chang-Oh JEONG

IPC: G02F1/1368 ,  H01L29/45 ,  G02F1/1362 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/49

CPC classification number: G02F1/1368 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136222 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/458 ,  H01L29/4908

Abstract: A thin film transistor substrate includes a base substrate and a thin film transistor. The base substrate includes a gate line and a data line. The thin film transistor is connected to the gate line and the data line. The thin film transistor includes a gate electrode, a semiconductor pattern and source, drain electrodes. The gate electrode is disposed on the base substrate. The semiconductor pattern overlaps with the gate electrode. The source, drain electrodes is spaced apart from each other. The source electrode includes a first source layer, a second source layer disposed on the first source layer and a first diffusion barrier disposed between the first source layer and second source layer. The drain electrode includes a first drain layer, a second drain layer disposed on the first drain layer and a second diffusion barrier disposed between the first drain layer and second drain layer.

Abstract translation: 薄膜晶体管基板包括基底基板和薄膜晶体管。 基板包括栅极线和数据线。 薄膜晶体管连接到栅极线和数据线。 薄膜晶体管包括栅电极，半导体图案和源极，漏极电极。 栅电极设置在基底基板上。 半导体图案与栅电极重叠。 源极，漏极彼此间隔开。 源电极包括第一源极层，设置在第一源极层上的第二源极层和设置在第一源极层和第二源极层之间的第一扩散阻挡层。 漏极包括第一漏极层，设置在第一漏极层上的第二漏极层和设置在第一漏极层和第二漏极层之间的第二扩散阻挡层。

公开(公告)号：US20150270118A1

公开(公告)日：2015-09-24

申请号：US14513463

申请日：2014-10-14

Applicant: Samsung Display Co., Ltd.

Inventor： Katsushi KISHIMOTO ,  Yeon-Keon MOON ,  Sang-Woo SOHN ,  Takayuki FUKASAWA ,  Sang-Won SHIN

IPC: H01L21/02 ,  C23C16/50 ,  C23C16/46

CPC classification number: C23C16/50 ,  C23C16/40 ,  C23C16/46 ,  C23C16/509 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/3105 ,  H01L21/67109 ,  H01L21/67207 ,  H01L21/67745 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: An oxide semiconductor depositing apparatus includes a heating chamber which is configured to heat and plasma-treat a first substrate including an insulation layer, and includes a chamber body, a heater disposed in the chamber body which is configured to heat the first substrate, and a cathode plate spaced apart from the heater, a high frequency voltage applied to the cathode plate, and a first process chamber which is configured to provide an oxide semiconductor layer on the insulation layer of the first substrate.

Abstract translation: 一种氧化物半导体沉积装置，包括加热室，其被配置为加热和等离子体处理包括绝缘层的第一基板，并且包括室主体，设置在室主体中的加热第一基板的加热器，以及 与加热器隔开的阴极板，施加到阴极板的高频电压，以及第一处理室，其被配置为在第一基板的绝缘层上提供氧化物半导体层。