Abstract:
A display device includes a plurality of pixel circuits and a gate driver including a plurality of stages configured to output a gate signal to a plurality of gate lines, respectively, to provide the gate signal to the pixel circuits. Each of the stages is divided into a plurality of sub-blocks. At least one of the pixel circuits is located between two adjacent sub-blocks of the sub-blocks.
Abstract:
A display device includes a substrate including a display region, a hole, and a hole edge region surrounding the hole, first data lines disposed on the substrate, extending in a first direction, arranged in a second direction intersecting the first direction in the display region, and bypassing the hole along the hole edge region, and second data lines disposed on the substrate, extending in the first direction, alternately arranged with the first data lines in the second direction in the display region, and bypassing the hole along the hole edge region. At least one of the first data lines intersects at least one of the second data lines such that the first data lines are disposed adjacent to each other and the second data lines are disposed adjacent to each other in the hole edge region.
Abstract:
A display device includes: a substrate including a main display portion, edge portions disposed at edges of the main display portion and including rounded corners, first side portions bent from the edge portions, and second side portions bent from the main display portion; scan lines and data lines that are disposed on the substrate; transistors connected to the scan lines and the data lines; and a data voltage transmission line connected to data lines that are disposed in the first side portions and the edge portions.
Abstract:
A display device including a flexible substrate that includes a display part to display an image; a driving integrated chip (IC) that supplies a driving voltage to the display part; a flexible printed circuit (FPC) attached to an outer side portion of the substrate; and a printed circuit board (PCB) attached to the FPC, the PCB transferring the driving voltage to the driving IC through the FPC, wherein the FPC includes attachment parts at ends thereof, the attachment parts of the FPC being attached to pad parts at the outer side portion of the substrate and to pad parts of the PCB, and the attachment parts include slits therein.
Abstract:
In a display device, a driving element is disposed on a rear substrate, and a passivation layer covers the driving element. A pixel electrode is disposed on the passivation layer and is connected to the driving element. An organic emission layer is disposed on the pixel electrode and is configured to emit tight toward the rear substrate. A common electrode is disposed on the organic emission layer. A touch electrode is disposed between the rear substrate and the passivation layer, and it forms a capacitive component when an external touch occurs.
Abstract:
Provided is a display device. The display apparatus includes a plurality of data lines, a data driver, a plurality of gate lines, gate drivers, wherein the gate drivers includes first gate drivers connected to one end of a first group of the plurality of gate lines and second drivers connected to the other end of a second group of the plurality of gate lines, compensation circuits for compensating a rising time and falling time of gate signals outputted from the gate drivers, wherein the compensation circuits includes first compensation circuits connected to the other end of the first group of the plurality of gate lines and second compensation circuits connected to one end of the second group of the plurality of gate lines; and a plurality of pixels are respectively disposed on areas between the gate drivers.
Abstract:
A display device includes a substrate including a display region, a hole, and a hole edge region surrounding the hole, first data lines disposed on the substrate, extending in a first direction, arranged in a second direction intersecting the first direction in the display region, and bypassing the hole along the hole edge region, and second data lines disposed on the substrate, extending in the first direction, alternately arranged with the first data lines in the second direction in the display region, and bypassing the hole along the hole edge region. At least one of the first data lines intersects at least one of the second data lines such that the first data lines are disposed adjacent to each other and the second data lines are disposed adjacent to each other in the hole edge region.
Abstract:
An organic light emitting display device includes first to third pixels arranged in a first direction, first to third gate lines respectively connected to the first to third pixels, first to third initialization control lines respectively connected to the first to third pixels, first to third light emission control lines respectively connected to the first to third pixels, a driving control signal supplying line connected to at least one of the first to third gate lines and at least one of the first to third initialization control lines, a light emission control signal supplying line connected to at least two of the first to third light emission control lines, a gate driver connected to the driving control signal supplying line, and a light emission control driver connected to the light emission control signal supplying line.
Abstract:
An organic light emitting display includes a plurality of pixels and a timing controller. The timing controller accumulates emission luminance values during a plurality of frames. The timing controller then supplies a reset signal to the pixels to respectively set non-emission periods for a plurality of subfields when the accumulated emission luminance value exceeds a reference value.
Abstract:
A display device includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction, a plurality of sub-gate lines corresponding to the plurality of gate lines and extending in a first direction to be adjacent to a corresponding gate line of the plurality of gate lines, a gate driver configured to drive the plurality of gate lines, a data driver configured to drive the plurality of data lines, and a plurality of pixels arranged in a display area, where an end of each of the plurality of gate lines extends in the first direction from the gate driver is electrically connected to a center portion of a corresponding sub-gate line in the first direction.