-
公开(公告)号：US20230230533A1
公开(公告)日：2023-07-20
申请号：US18066111
申请日：2022-12-14
Applicant: Samsung Display Co., LTD.
Inventor： Hyun Joon KIM , Kye Uk LEE , Sang Jin JEON , Jung Hwan HWANG
CPC classification number: G09G3/32 , H01L25/167 , H01L27/124 , G09G2300/0426 , G09G2300/0819 , G09G2300/026 , H01L24/05
Abstract: A display device includes a scan write line configured to receive a scan write signal, a scan initialization line configured to receive a scan initialization signal, a sweep signal line configured to receive a sweep signal, a first data line configured to receive a first data voltage, a second data line configured to receive a second data voltage, and a subpixel connected to the scan write line, the scan initialization line, the sweep signal line, the first data line, and the second data line. The subpixel includes a light-emitting element, a first pixel driver including a first transistor configured to generate a control current according to the first data voltage of the first data line, and a second pixel driver including an eighth transistor configured to generate a driving current applied to the light-emitting element according to the second data voltage.
-
公开(公告)号：US20230121681A1
公开(公告)日：2023-04-20
申请号：US17807690
申请日：2022-06-17
Applicant: Samsung Display Co., LTD.
Inventor： Jung Hwan HWANG , Hyun Joon KIM , Kye Uk LEE , Sang Jin JEON , Jun Ki JEONG
IPC: G09G3/32
Abstract: A display device includes a scan write line, a PWM emission line, a PAM emission line, a sweep signal line, a first data line, a second data line, and a subpixel connected thereto, and including a light emitting element, a first pixel driver to supply a control current to a node according to the first data voltage in response to the PWM emission signal, a second pixel driver to generate a driving current according to the second data voltage in response to the PWM emission signal, and a third pixel driver to supply the driving current to the light emitting element according to the PAM emission signal and a voltage of the node, wherein the PWM emission signal includes a plurality of PWM pulses, the PAM emission signal includes a plurality of PAM pulses, and a number of the PWM pulses is greater than a number of the PAM pulses.
-
公开(公告)号：US20230119036A1
公开(公告)日：2023-04-20
申请号：US17849277
申请日：2022-06-24
Applicant: Samsung Display Co., LTD.
Inventor： Jung Hwan HWANG , Hyun Joon KIM , Kye Uk LEE , Sang Jin JEON , Jun Ki JEONG
IPC: G09G3/22
Abstract: A display device includes a first pixel driver connected to a sweep line, the first pixel driver generating a control current based on a first data voltage, a second pixel driver connected to a scan control line, the second pixel driver generating a driving current based on a second data voltage and controlling a period for which the driving current flows, based on the control current, and a light-emitting element connected to the second pixel driver to receive the driving current. The first pixel driver includes a first transistor generating the control current based on the first data voltage, a second transistor providing the first data voltage to a first electrode of the first transistor based on a scan write signal, and a first capacitor including a first capacitor electrode connected to a gate electrode of the first transistor, and a second capacitor electrode connected to the sweep line.
-
公开(公告)号：US20230082959A1
公开(公告)日：2023-03-16
申请号：US17842927
申请日：2022-06-17
Applicant: Samsung Display Co., LTD.
Inventor： Jun Ki JEONG , Hyun Joon KIM , Kye Uk LEE , Sang Jin JEON , Jung Hwan HWANG
IPC: G09G3/32
Abstract: A display device includes a display area which displays an image, and a non-display area disposed around the display area and including a pad part. The display area includes pixels of a first pixel row which are pixels arranged in a first direction along the first pixel row, pixels of a second pixel row, which are pixels arranged in the first direction along the second pixel row next to the first pixel row, and pixel circuits of a first circuit row which are pixel circuits arranged in the first direction along the first circuit row, where the pixel circuits of the first circuit row are electrically connected to the pixels of the first pixel row, respectively. The first pixel row and the first circuit row are spaced apart from each other with the second pixel row interposed therebetween.
-
公开(公告)号：US20170084708A1
公开(公告)日：2017-03-23
申请号：US15369008
申请日：2016-12-05
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Bon-Yong KOO , Soo Jin PARK , Jong-Moon PARK , Yong Hee LEE , Jong-Hyuk LEE , Duc-Han CHO
IPC: H01L29/417 , H01L27/12
CPC classification number: H01L29/41733 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L29/41775
Abstract: A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.
-
Patent Agency Ranking
公开(公告)号：US20230252932A1
公开(公告)日：2023-08-10
申请号：US18135212
申请日：2023-04-17
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Beom Jun KIM , Seong Yeol SYN , Bong-Jun LEE , You Mee HYUN
CPC classification number: G09G3/2092 , G09G3/3648 , G09G3/3677 , G11C19/28 , G09G2310/0286 , G09G2300/0809
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
-
公开(公告)号：US20230246148A1
公开(公告)日：2023-08-03
申请号：US17965511
申请日：2022-10-13
Applicant: Samsung Display Co., LTD.
Inventor： Kye Uk LEE , Hyun Joon KIM , Jung Hwan HWANG
CPC classification number: H01L33/62 , G09F9/33 , G09F9/3026 , H01L27/0288 , H01L33/382
Abstract: A display device includes a substrate including a display area including pixels, and a non-display area around the display area, a pad part in the non-display area, antistatic circuits between the pad part and the pixels, respectively, a first resistance line connected to the pad part and to the antistatic circuits, a second resistance line connected to the first resistance line and overlapping the first resistance line, and a fan-out line connected between the second resistance line and a respective one of the pixels.
-
公开(公告)号：US20230238493A1
公开(公告)日：2023-07-27
申请号：US17894536
申请日：2022-08-24
Applicant: Samsung Display Co., LTD.
Inventor： Kye Uk LEE , Hyun Joon KIM , Jung Hwan HWANG
CPC classification number: H01L33/62 , H01L27/156 , H01L33/382 , G09F9/3026 , G09F9/33
Abstract: A display device includes a display area including light emitting elements in a first pixel row, pixel circuits in a first circuit row and electrically connected to the first pixel row, light emitting elements in a second pixel row between the first pixel row and the first circuit row, pixel circuits in a second circuit row and electrically connected to the second pixel row, and a gate driver including a first stage disposed between the pixel circuits of the first circuit row and a second stage disposed between the pixel circuits of the second circuit row. A distance between adjacent pixel circuits with the first stage between the adjacent pixel circuits in the first circuit row is greater than a distance between other pixel circuits of the first circuit row.
-
公开(公告)号：US20200020269A1
公开(公告)日：2020-01-16
申请号：US16583018
申请日：2019-09-25
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Beom Jun KIM , Seong Yeol SYN , Bong-Jun LEE , You Mee HYUN
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
-
公开(公告)号：US20240071299A1
公开(公告)日：2024-02-29
申请号：US18498018
申请日：2023-10-30
Applicant: Samsung Display Co., LTD.
Inventor： Jung Hwan HWANG , Hyun Joon KIM , Kye Uk LEE , Jun Ki JEONG , Sang Jin JEON
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/027 , G09G2310/0297
Abstract: A display device includes connection lines, pulse amplitude modulation (PAM) data lines configured to receive pulse width modulation (PWM) data voltages, PWM data lines configured to receive the PWM data voltages, a first connection control line configured to receive a first connection control signal, a second connection control line configured to receive a second connection control signal, subpixels connected to the PWM data lines and the PAM data lines, and a first demultiplexer (demux) unit configured to connect the connection lines to the PAM data lines or to the PWM data lines according to the first connection control signal and the second connection control signal.
-
-
-
-
-
-
-
-
-
Search Results
40
records
(took 0.017 seconds)
