公开(公告)号：US09666602B2

公开(公告)日：2017-05-30

申请号：US13828990

申请日：2013-03-14

Applicant: Samsung Display Co., LTD.

Inventor： Ji-Seon Lee ,  Dong-Jo Kim ,  Yoon-Ho Khang ,  Yong-Su Lee ,  Jong-Chan Lee

IPC: H01L33/08 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1222 ,  H01L27/124 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor substrate includes the following elements: a base substrate, a data line disposed on the base substrate, a source electrode contacting the data line, a drain electrode spaced from the source electrode, a channel disposed between the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a gate insulation pattern disposed on the channel, and a gate electrode disposed on the gate insulation pattern.

公开(公告)号：US09281343B2

公开(公告)日：2016-03-08

申请号：US13761930

申请日：2013-02-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong-Su Lee ,  Yoon-Ho Khang ,  Se-Hwan Yu ,  Dong-Jo Kim ,  Min-Jung Lee

IPC: H01L27/12 ,  H01L27/15 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: H01L27/156 ,  G02F1/13458 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248

Abstract: A thin film transistor display panel includes: a gate electrode, a source electrode and a drain electrode which are included in a thin film transistor on a substrate; a data line connected to the source electrode; a pixel link member connecting the drain electrode to a pixel electrode; and a gate pad connected to the gate electrode through a gate line and including a first gate subpad, a second gate subpad and a gate pad link member, in which the pixel link member and the gate pad link member are substantially same in thickness.

Abstract translation: 薄膜晶体管显示面板包括：栅电极，源电极和漏电极，其包括在基板上的薄膜晶体管中; 连接到源电极的数据线; 将漏电极连接到像素电极的像素连接构件; 以及栅极焊盘，其通过栅极线连接到栅电极，并且包括第一栅极子板，第二栅极子板和栅极焊盘连接部件，其中像素连接部件和栅极焊盘连接部件的厚度基本相同。

公开(公告)号：US09252284B2

公开(公告)日：2016-02-02

申请号：US14182989

申请日：2014-02-18

Applicant: Samsung Display Co., Ltd.

Inventor： Jong-Chan Lee ,  Yoon-Ho Khang ,  Su-Hyoung Kang ,  Dong-Jo Kim ,  Ji-Seon Lee ,  Myoung-Geun Cha ,  Deuk-Myung Ji

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693

Abstract: A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.

Abstract translation: 公开了显示基板和显示基板的制造方法。 在该方法中，在基底基板上形成栅电极。 使用氧化物半导体形成有源图案。 有源图案部分地与栅电极重叠。 在活性图案上依次形成第一绝缘层图案和第二绝缘层图案。 第一绝缘层图案和第二绝缘层图案与栅电极重叠。 形成第三绝缘层以覆盖有源图案，第一绝缘层图案和第二绝缘层图案。 第一绝缘层图案或第二绝缘层图案都包括氧化铝。 形成第一绝缘层图案和第二绝缘层图案包括使用栅电极进行背面曝光处理作为曝光掩模。

公开(公告)号：US20150060843A1

公开(公告)日：2015-03-05

申请号：US14182989

申请日：2014-02-18

Applicant: Samsung Display Co., Ltd.

Inventor： Jong-Chan LEE ,  Yoon-Ho Khang ,  Su-Hyoung Kang ,  Dong-Jo Kim ,  Ji-Seon Lee ,  Myoung-Geun Cha ,  Deuk-Myung Ji

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693

Abstract: A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.

Abstract translation: 公开了显示基板和显示基板的制造方法。 在该方法中，在基底基板上形成栅电极。 使用氧化物半导体形成有源图案。 有源图案部分地与栅电极重叠。 在活性图案上依次形成第一绝缘层图案和第二绝缘层图案。 第一绝缘层图案和第二绝缘层图案与栅电极重叠。 形成第三绝缘层以覆盖有源图案，第一绝缘层图案和第二绝缘层图案。 第一绝缘层图案或第二绝缘层图案都包括氧化铝。 形成第一绝缘层图案和第二绝缘层图案包括使用栅电极进行背面曝光处理作为曝光掩模。

公开(公告)号：US09356153B2

公开(公告)日：2016-05-31

申请号：US14452261

申请日：2014-08-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yoon-Ho Khang ,  Dong-Jo Kim ,  Su-Hyoung Kang ,  Yong-Su Lee

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

Abstract: A thin film transistor includes a bottom gate electrode, a top gate electrode and an active pattern. The top gate electrode includes a transparent conductive material and overlaps with the bottom gate electrode. A boundary of the bottom gate electrode and a boundary of the top gate electrode are coincident with each other in a cross-sectional view. The active pattern includes a source portion, a drain portion and a channel portion disposed between the source portion and the drain portion. The channel portion overlaps with the bottom gate electrode and the top gate electrode.

Abstract translation: 薄膜晶体管包括底栅电极，顶栅电极和有源图案。 顶栅电极包括透明导电材料并与底栅电极重叠。 底栅电极的边界和顶栅电极的边界在横截面图中彼此重合。 有源图案包括源极部分，漏极部分和设置在源极部分和漏极部分之间的沟道部分。 沟道部分与底栅电极和顶栅电极重叠。

公开(公告)号：US20140239295A1

公开(公告)日：2014-08-28

申请号：US14190722

申请日：2014-02-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae-Woo PARK ,  Dong-Jo Kim ,  Ju-Ok Park ,  In-Sung Sohn ,  Sang-Won Yoon ,  Gun-Hyo Lee ,  Yong-Jin Lee ,  Yoon-Gyu Lee ,  Do-Hyun Kim ,  Woo-Seok Jeon

IPC: H01L29/786 ,  C23C14/34

CPC classification number: H01L29/7869 ,  C23C14/3414

Abstract: Provided are a zinc oxide-based sputtering target, a method of preparing the same, and a thin film transistor including a barrier layer deposited by the zinc oxide-based sputtering target. The zinc oxide-based sputtering target includes a sintered body that is composed of zinc oxide in which indium oxide is doped in a range from about 1% w/w to about 50% w/w. A backing plate is coupled to a back of the sintered body. The backing plate supports the sintered body.

Abstract translation: 提供了一种基于氧化锌的溅射靶，其制备方法和包含由氧化锌基溅射靶沉积的势垒层的薄膜晶体管。 基于氧化锌的溅射靶包括由氧化锌组成的烧结体，其中氧化铟掺杂在约1％w / w至约50％w / w的范围内。 背板联接到烧结体的背面。 背板支撑烧结体。