公开(公告)号：US20130229863A1

公开(公告)日：2013-09-05

申请号：US13771663

申请日：2013-02-20

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino CONTE ,  Maria GIAQUINTA ,  Loredana CHIARAMONTE

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C5/145 ,  G11C5/147 ,  G11C13/0038 ,  G11C13/0069

Abstract: A driving stage for a phase change non-volatile memory device may have an output driving unit which supplies an output driving current during an operation of programming of at least one memory cell. A driving-control unit receives an input current and generates at output a first control signal that controls supply of the output driving current by the output driving unit in such a way that a value of this current has a desired relation with the input current. A level-shifter element, set between the output of the driving-control unit and a control input of the output driving unit, determines a level shift of the voltage of the first control signal so as to supply to the control input of the output driving unit a second control signal, having a voltage value that is increased with respect to, and is a function of, the first control signal.

Abstract translation: 用于相变非易失性存储器件的驱动级可以具有输出驱动单元，其在至少一个存储器单元的编程操作期间提供输出驱动电流。 驱动控制单元接收输入电流并在输出端产生控制由输出驱动单元输出驱动电流的供给的第一控制信号，使得该电流的值与输入电流具有期望的关系。 设置在驱动控制单元的输出和输出驱动单元的控制输入之间的电平移动元件确定第一控制信号的电压的电平偏移，以便提供给输出驱动的控制输入 单元具有第二控制信号，具有相对于第一控制信号而增加并且是第一控制信号的函数的电压值。

公开(公告)号：US20160314841A1

公开(公告)日：2016-10-27

申请号：US15198161

申请日：2016-06-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino CONTE ,  Maria GIAQUINTA

IPC: G11C16/06 ,  H03F3/45 ,  H03M1/66

CPC classification number: G11C16/06 ,  H03F1/34 ,  H03F3/347 ,  H03F3/45 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2200/156 ,  H03F2200/375 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/45332 ,  H03F2203/45514 ,  H03F2203/45546 ,  H03F2203/45632 ,  H03M1/661

Abstract: A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.