公开(公告)号：US20160285509A1

公开(公告)日：2016-09-29

申请号：US14984966

申请日：2015-12-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Yoann BOUVET ,  Pierre DEMAJ

IPC: H04B3/54 ,  H04L27/26 ,  H04L5/00

CPC classification number: H04B3/54 ,  H04L5/0007 ,  H04L25/03993 ,  H04L25/067 ,  H04L27/2607 ,  H04L27/2656 ,  H04L27/2675 ,  H04L27/2691

Abstract: A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.

Abstract translation: 一种用于处理来自传输信道的模拟信号的方法。 模拟信号可以包括调制在载波子集上的有用信号。 该方法可以包括将模拟信号模数转换为数字信号，并对数字信号进行同步处理。 同步可以包括在时域中从数字信号的自回归模型中确定预测滤波器的有限数量的系数，并且通过数字有限脉冲响应滤波器在时域中对数字信号进行滤波，其中系数基于 有限数量的系数提供一个滤波后的数字信号。 该方法可以包括使用滤波的数字信号和参考信号来检测允许帧结构中的位置被识别的指示。

公开(公告)号：US20240014819A1

公开(公告)日：2024-01-11

申请号：US17861067

申请日：2022-07-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Jean-Francois LINK ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/17736 ,  H03K19/173 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1737 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US20230353154A1

公开(公告)日：2023-11-02

申请号：US17733934

申请日：2022-04-29

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17736 ,  H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1774

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

公开(公告)号：US20240267050A1

公开(公告)日：2024-08-08

申请号：US18641199

申请日：2024-04-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17736 ,  H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1774

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

公开(公告)号：US20240178842A1

公开(公告)日：2024-05-30

申请号：US18435913

申请日：2024-02-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Jean-Francois LINK ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US20230387917A1

公开(公告)日：2023-11-30

申请号：US17827515

申请日：2022-05-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17704 ,  H03K19/096 ,  H03K3/0233

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/17708 ,  H03K19/096 ,  H03K3/0233

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

公开(公告)号：US20160359505A1

公开(公告)日：2016-12-08

申请号：US14961985

申请日：2015-12-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS

IPC: H04B1/00 ,  H04L5/00 ,  H04B3/54

CPC classification number: H04B1/0007 ,  H04B3/54 ,  H04B2203/5425 ,  H04L5/001

Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.

Abstract translation: 一种方法包括通过信息调制的数字信号的数字/模拟转换，以提供具有大于1的波峰因数的调制初始模拟信号，以及初始模拟信号的放大以提供放大的调制信号。 从调制的放大模拟信号导出的调制信道模拟信号通过通信信道发送，通信信道的阻抗在传输期间变化。 该方法还包括在至少一个时间间隔期间传输放大的模拟信号的峰值限幅率期间的至少一个确定，以及作为确定的峰值限幅率的函数的初始模拟信号的电平的调整 。