Abstract:
An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.
Abstract:
The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method for transmitting a signal in a signal transmitting apparatus in a communication system supporting a bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme is provided. The method includes performing an outer encoding operation; performing an interleaving operation on the outer code corresponding to an interleaving scheme which is based on a preset generation matrix to generate an interleaved signal; performing an inner encoding operation; performing a modulating operation; and transmitting the modulated signal, wherein the generation matrix is generated by applying at least one of a preset column permutation rule and a preset row permutation rule to a generation matrix for a quasi-cyclic (QC) interleaver.